Florent Kermarrec d77a5fc5ac fhdl/specials: add Keep SynthesisDirective		2015-06-23 16:14:42 +02:00
..
actorlib
bank
bus	bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)	2015-06-19 08:37:16 +02:00
fhdl	fhdl/specials: add Keep SynthesisDirective	2015-06-23 16:14:42 +02:00
flow
genlib	migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)	2015-06-02 19:26:42 +02:00
sim
test	add examples tests	2015-05-01 00:50:17 +08:00
util
__init__.py