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3f7f0a3151
litex
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misoclib
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mem
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example_designs
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Florent Kermarrec
04c64eb1d8
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00
..
kc705.py
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
verilog_backend.py
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00