87 lines
3.1 KiB
Python
87 lines
3.1 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Wolfgang Nagele <mail@wnagele.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.cores.led import WS2812
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class TestWS2812(unittest.TestCase):
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test_clk_freqs = [75e6, 50e6, 25e6]
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def generator(self, dut, led_signal, led_data, sys_clk_freq, iterations):
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# Error Margin from WS2812 datasheet.
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error_margin = 150e-9
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# Cap on how long a sequence will be evaluated.
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max_cycles_per_seq = int(dut.trst * sys_clk_freq * 2)
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# Verify initial reset.
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rst_cycles = 0
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for _ in range(max_cycles_per_seq):
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if (yield led_signal) != 0:
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break
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rst_cycles += 1
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yield
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rst_time = rst_cycles / sys_clk_freq
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assert rst_time >= dut.trst
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# Verify generated data pulses.
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length = len(led_data)
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for _ in range(iterations):
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for i_num, num in enumerate(led_data, start=1):
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for idx_bit, bit in enumerate(TestWS2812.to_bits(num), start=1):
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exp_high, exp_low = {
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0 : (dut.t0h, dut.t0l),
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1 : (dut.t1h, dut.t1l)
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}[bit]
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# On end of chain, add reset time to exp_low
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if i_num == length and idx_bit == 24:
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exp_low += dut.trst
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# Verify high cycle.
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high_cycles = 0
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for _ in range(max_cycles_per_seq):
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if (yield led_signal) != 1:
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break
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high_cycles += 1
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yield
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high_time = high_cycles / sys_clk_freq
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assert high_time >= exp_high - error_margin
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assert high_time <= exp_high + error_margin
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# Verify low cycle.
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low_cycles = 0
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for _ in range(max_cycles_per_seq):
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if (yield led_signal) != 0:
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break
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low_cycles += 1
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yield
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low_time = low_cycles / sys_clk_freq
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assert low_time >= exp_low - error_margin
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assert low_time <= exp_low + error_margin
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def to_bits(num, length = 24):
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return ( int(x) for x in bin(num)[2:].zfill(length) )
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def run_test(self, revision, sys_clk_freq):
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led_signal = Signal()
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led_data = [0x100000, 0x200000, 0x300000, 0x400000, 0x500000, 0x600000, 0x700000, 0x800000, 0x900000]
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iterations = 2
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dut = WS2812(led_signal, len(led_data), sys_clk_freq, revision=revision, init=led_data)
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run_simulation(dut, self.generator(dut, led_signal, led_data, sys_clk_freq, iterations), vcd_name="sim.vcd")
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def test_WS2812_old(self):
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for sys_clk_freq in self.test_clk_freqs:
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self.run_test("old", sys_clk_freq)
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def test_WS2812_new(self):
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for sys_clk_freq in self.test_clk_freqs:
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self.run_test("new", sys_clk_freq) |