Florent Kermarrec a1e4183b3f sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY		2015-08-22 12:50:41 +02:00
..
core	sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon	2015-06-17 15:30:30 +02:00
frontend	wishbone2lasmi: fix "READ_DATA" state	2015-07-09 10:40:32 +02:00
phy	sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY	2015-08-22 12:50:41 +02:00
test	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	global: pep8 (replace tabs with spaces)	2015-04-13 16:19:55 +02:00
module.py	sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis, Novena) modules.	2015-08-22 12:42:44 +02:00