Andrew Dennison 67e6614eb2 test_i2c: whitespace cleanups		2024-07-20 15:45:44 +10:00
..
__init__.py	…
test_avalon_mm.py	…
test_axi.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_lite.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_stream.py	…
test_bitbang.py	…
test_clock.py	cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.	2022-01-25 11:09:15 +01:00
test_code_8b10b.py	…
test_cpu.py	test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).	2024-05-14 12:53:09 +02:00
test_csr.py	csr_bus: Honour re signal from the upstream bus	2024-06-23 19:35:19 +01:00
test_ecc.py	…
test_emif.py	…
test_fifosyncmacro.py	…
test_gearbox.py	…
test_hyperbus.py	test/test_hyperbus: Update.	2024-04-16 11:12:30 +02:00
test_i2c.py	test_i2c: whitespace cleanups	2024-07-20 15:45:44 +10:00
test_i2s.py	…
test_icap.py	…
test_led.py	…
test_packet.py	…
test_prbs.py	…
test_reduce.py	…
test_spi.py	…
test_spi_mmap.py	test/spi_mmap: be less verbose	2024-04-05 12:35:47 +11:00
test_spi_opi.py	…
test_stream.py	…
test_timer.py	…
test_wishbone.py	test/test_wishbone: Improve origin_region_remap_test to test more complex remapping.	2024-02-28 19:11:55 +01:00