Sebastien Bourdeauducq 41e2430e2b fhdl: automatic signal name from assignment		2011-12-18 21:26:51 +01:00
..
bank	bank: support raw registers	2011-12-18 00:28:04 +01:00
bus	32-device, 8-bit CSR bus	2011-12-17 15:54:49 +01:00
corelogic	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
fhdl	fhdl: automatic signal name from assignment	2011-12-18 21:26:51 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00