324 lines
7.6 KiB
Python
324 lines
7.6 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migen.genlib.misc import optree
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from migen.genlib.fsm import *
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from miscope.tools.misc import RisingEdge
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class Storage:
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#
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# Definition
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#
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def __init__(self, width, depth):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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# Control
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self.rst = Signal()
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self.start = Signal()
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self.offset = Signal(self.depth_width)
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self.size = Signal(self.depth_width)
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self.done = Signal()
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# Push Path
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self.push_stb = Signal()
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self.push_dat = Signal(self.width)
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self._push_ptr = Signal(self.depth_width)
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self._push_ptr_stop = Signal(self.depth_width)
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# Pull Path
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self.pull_stb = Signal()
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self.pull_dat = Signal(self.width)
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self._pull_ptr = Signal(self.depth_width)
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# Memory
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self._mem = Memory(self.width, self.depth)
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self._push_port = self._mem.get_port(write_capable=True)
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self._pull_port = self._mem.get_port(has_re=True)
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def get_fragment(self):
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comb = [
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self._push_port.adr.eq(self._push_ptr),
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self._push_port.we.eq(self.push_stb),
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self._push_port.dat_w.eq(self.push_dat),
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self._pull_port.adr.eq(self._pull_ptr),
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self._pull_port.re.eq(self.pull_stb),
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self.pull_dat.eq(self._pull_port.dat_r)
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]
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# FSM
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fsm = FSM("IDLE", "ACTIVE")
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# Idle
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fsm.act(fsm.IDLE,
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If(self.start,
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fsm.next_state(fsm.ACTIVE),
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)
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)
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# Active
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fsm.act(fsm.ACTIVE,
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If(self.done | self.rst,
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fsm.next_state(fsm.IDLE),
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)
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)
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sync =[
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If(fsm.entering(fsm.ACTIVE),
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self._push_ptr_stop.eq(self._push_ptr + self.size - self.offset),
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self._pull_ptr.eq(self._push_ptr - self.offset - 1)
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).Else(
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If(self.pull_stb, self._pull_ptr.eq(self._pull_ptr + 1))
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),
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If(self.push_stb, self._push_ptr.eq(self._push_ptr + 1)),
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]
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comb +=[self.done.eq((self._push_ptr == self._push_ptr_stop) & fsm.ongoing(fsm.ACTIVE))]
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return Fragment(comb, sync, specials={self._mem}) + fsm.get_fragment()
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class RLE:
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#
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# Definition
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#
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def __init__(self, width, length):
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self.width = width
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self.length = length
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# Control
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self.enable = Signal()
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# Input
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self.stb_i = Signal()
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self.dat_i = Signal(width)
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# Output
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self.stb_o = Signal()
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self.dat_o = Signal(width)
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def get_fragment(self):
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# Register Input
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stb_i_d = Signal()
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dat_i_d = Signal(self.width)
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sync =[dat_i_d.eq(self.dat_i)]
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sync +=[stb_i_d.eq(self.stb_i)]
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# Detect diff
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diff = Signal()
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comb = [diff.eq(self.stb_i & (~self.enable | (dat_i_d != self.dat_i)))]
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diff_rising = RisingEdge(diff)
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diff_d = Signal()
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sync +=[diff_d.eq(diff)]
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# Generate RLE word
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rle_cnt = Signal(max=self.length)
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rle_max = Signal()
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comb +=[If(rle_cnt == self.length, rle_max.eq(self.enable))]
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sync +=[
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If(diff | rle_max,
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rle_cnt.eq(0)
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).Else(
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rle_cnt.eq(rle_cnt + 1)
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)
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]
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# Mux RLE word and data
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comb +=[
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If(diff_rising.o & (~rle_max),
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self.stb_o.eq(1),
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self.dat_o[self.width-1].eq(1),
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self.dat_o[:len(rle_cnt)].eq(rle_cnt)
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).Elif(diff_d | rle_max,
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self.stb_o.eq(stb_i_d),
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self.dat_o.eq(dat_i_d)
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).Else(
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self.stb_o.eq(0),
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)
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]
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return Fragment(comb, sync) + diff_rising.get_fragment()
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class Sequencer:
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#
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# Definition
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#
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def __init__(self):
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# Control
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self.rst = Signal()
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self.arm = Signal()
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# Trigger
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self.hit = Signal()
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# Recorder
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self.start = Signal()
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self.done = Signal()
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# Internal
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self.enable = Signal()
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def get_fragment(self):
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# FSM
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fsm = FSM("IDLE", "ACTIVE")
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# Idle
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fsm.act(fsm.IDLE,
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If(self.arm,
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fsm.next_state(fsm.ACTIVE),
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)
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)
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# Active
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fsm.act(fsm.ACTIVE,
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If(self.done | self.rst,
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fsm.next_state(fsm.IDLE),
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),
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self.enable.eq(1)
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)
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# Start
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hit_rising = RisingEdge(self.hit)
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comb =[self.start.eq(self.enable & hit_rising.o)]
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return Fragment(comb) + fsm.get_fragment() + hit_rising.get_fragment()
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REC_RST_BASE = 0x00
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REC_RLE_BASE = 0x01
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REC_ARM_BASE = 0x02
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REC_DONE_BASE = 0x03
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REC_SIZE_BASE = 0x04
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REC_OFFSET_BASE = 0x06
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REC_READ_BASE = 0x08
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REC_READ_DATA_BASE = 0x09
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class Recorder:
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#
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# Definition
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#
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def __init__(self, width, depth, address=0x0000, interface=None):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth-1)
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self.storage = Storage(self.width, self.depth)
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self.sequencer = Sequencer()
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self.rle = RLE(self.width, (2**(width-2)))
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# csr interface
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self._r_rst = RegisterField(reset=1)
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self._r_rle = RegisterField(reset=0)
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self._r_arm = RegisterField(reset=0)
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self._r_done = RegisterField(reset=0, access_bus=READ_ONLY,
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access_dev=WRITE_ONLY)
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self._r_size = RegisterField(self.depth_width, reset=1)
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self._r_offset = RegisterField(self.depth_width, reset=1)
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self._r_pull_stb = RegisterField(reset=0)
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self._r_pull_dat = RegisterField(self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self.regs = [self._r_rst, self._r_rle, self._r_arm, self._r_done, self._r_size, self._r_offset,
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self._r_pull_stb, self._r_pull_dat]
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# set address / interface
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self.set_address(address)
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self.set_interface(interface)
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# trigger Interface
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self.hit = Signal()
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self.stb = Signal()
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self.dat = Signal(self.width)
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def set_address(self, address):
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self.address = address
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self.bank = csrgen.Bank(self.regs, address=self.address)
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def set_interface(self, interface):
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self.interface = interface
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def get_fragment(self):
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_pull_stb_rising = RisingEdge(self._r_pull_stb.field.r)
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# Bank <--> Storage / Sequencer
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comb = [
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self.sequencer.rst.eq(self._r_rst.field.r),
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self.storage.rst.eq(self._r_rst.field.r),
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self.rle.enable.eq(self._r_rle.field.r),
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self.sequencer.arm.eq(self._r_arm.field.r),
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self.storage.offset.eq(self._r_offset.field.r),
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self.storage.size.eq(self._r_size.field.r),
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self._r_done.field.w.eq(~self.sequencer.enable),
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self.storage.pull_stb.eq(_pull_stb_rising.o),
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self._r_pull_dat.field.w.eq(self.storage.pull_dat)
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]
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# Storage <--> Sequencer <--> Trigger
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comb += [
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self.storage.start.eq(self.sequencer.start),
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self.sequencer.done.eq(self.storage.done),
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self.sequencer.hit.eq(self.hit),
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self.rle.stb_i.eq(self.stb),
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self.rle.dat_i.eq(self.dat),
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self.storage.push_stb.eq(self.sequencer.enable & self.rle.stb_o),
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self.storage.push_dat.eq(self.rle.dat_o)
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]
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return self.bank.get_fragment() + Fragment(comb) +\
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self.storage.get_fragment() + self.sequencer.get_fragment() +\
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_pull_stb_rising.get_fragment() + self.rle.get_fragment()
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#
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# Driver
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#
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def reset(self):
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self.interface.write(self.bank.get_base() + REC_RST_BASE, 1)
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self.interface.write(self.bank.get_base() + REC_RST_BASE, 0)
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def enable_rle(self):
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self.interface.write(self.bank.get_base() + REC_RLE_BASE, 1)
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def disable_rle(self):
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self.interface.write(self.bank.get_base() + REC_RLE_BASE, 0)
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def arm(self):
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self.interface.write(self.bank.get_base() + REC_ARM_BASE, 1)
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self.interface.write(self.bank.get_base() + REC_ARM_BASE, 0)
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def is_done(self):
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return self.interface.read(self.bank.get_base() + REC_DONE_BASE) == 1
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def set_size(self, dat):
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self.interface.write_n(self.bank.get_base() + REC_SIZE_BASE, dat, 16)
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def set_offset(self, dat):
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self.interface.write_n(self.bank.get_base() + REC_OFFSET_BASE, dat, 16)
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def pull(self, size):
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r = []
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for i in range(size):
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self.interface.write(self.bank.get_base() + REC_READ_BASE, 1)
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self.interface.write(self.bank.get_base() + REC_READ_BASE, 0)
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r.append(self.interface.read_n(self.bank.get_base() + REC_READ_DATA_BASE, self.width))
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return r
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