Florent Kermarrec 42efa99826 SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.		2020-01-15 10:59:01 +01:00
..
cores	cores/uart/UARTInterface: remove connect method	2020-01-13 16:58:00 +01:00
integration	SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.	2020-01-15 10:59:01 +01:00
interconnect	wishbone/Cache: avoid REFILL_WRTAG state to improve speed.	2020-01-10 14:25:07 +01:00
software	bios/sdram: switch to updated CSR accessors, and misc. cleanup	2020-01-13 10:09:02 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00