153 lines
5.3 KiB
Python
153 lines
5.3 KiB
Python
from migen.build.generic_platform import *
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from migen.build.xilinx import XilinxPlatform
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from migen.build.xilinx.programmer import UrJTAG
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_io = [
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("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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("user_led", 1, Pins("A16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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("user_btn", 0, Pins("AB4"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("AA4"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("AB5"), IOStandard("LVCMOS33")),
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("clk50", 0, Pins("AB11"), IOStandard("LVCMOS33")),
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# When executing softcore code in-place from the flash, we want
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# the flash reset to be released before the system reset.
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("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)),
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("norflash", 0,
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Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22",
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"F21 K17 J17 E22 E20 H18 H19 F20",
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"G19 C22 C20 D22 D21 F19 F18 D20 D19")),
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Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7",
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"AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")),
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Subsignal("oe_n", Pins("M22")),
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Subsignal("we_n", Pins("N20")),
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Subsignal("ce_n", Pins("M21")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)
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),
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("serial", 0,
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Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP"))
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),
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("ddram_clock", 0,
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Subsignal("p", Pins("M3")),
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Subsignal("n", Pins("L4")),
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IOStandard("SSTL2_I")
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),
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("ddram", 0,
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Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")),
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Subsignal("ba", Pins("A2 E6")),
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Subsignal("cs_n", Pins("F7")),
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Subsignal("cke", Pins("G7")),
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Subsignal("ras_n", Pins("E5")),
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Subsignal("cas_n", Pins("C4")),
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Subsignal("we_n", Pins("D3")),
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Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
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"U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
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"M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")),
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Subsignal("dm", Pins("E1 E3 F3 G4")),
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Subsignal("dqs", Pins("F1 F2 H5 H6")),
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IOStandard("SSTL2_I")
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),
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("eth_clocks", 0,
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Subsignal("phy", Pins("M20")),
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Subsignal("rx", Pins("H22")),
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Subsignal("tx", Pins("H21")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R22")),
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Subsignal("dv", Pins("V21")),
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Subsignal("rx_er", Pins("V22")),
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Subsignal("rx_data", Pins("U22 U20 T22 T21")),
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Subsignal("tx_en", Pins("N19")),
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Subsignal("tx_er", Pins("M19")),
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Subsignal("tx_data", Pins("M16 L15 P19 P20")),
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Subsignal("col", Pins("W20")),
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Subsignal("crs", Pins("W22")),
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IOStandard("LVCMOS33")
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),
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("vga_out", 0,
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Subsignal("clk", Pins("A11")),
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Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")),
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Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")),
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Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")),
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Subsignal("hsync_n", Pins("A14")),
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Subsignal("vsync_n", Pins("C15")),
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Subsignal("psave_n", Pins("B14")),
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IOStandard("LVCMOS33")
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),
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("mmc", 0,
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Subsignal("clk", Pins("A10")),
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Subsignal("cmd", Pins("B18")),
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Subsignal("dat", Pins("A18 E16 C17 A17")),
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IOStandard("LVCMOS33")
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),
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# Digital video mixer extension board
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("dvi_in", 0,
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Subsignal("clk", Pins("A20")),
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Subsignal("data0_n", Pins("A21")),
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Subsignal("data1", Pins("B21")),
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Subsignal("data2_n", Pins("B22")),
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Subsignal("scl", Pins("G16")),
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Subsignal("sda", Pins("G17")),
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IOStandard("LVCMOS33")
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),
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("dvi_in", 1,
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Subsignal("clk", Pins("H17")),
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Subsignal("data0_n", Pins("H16")),
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Subsignal("data1", Pins("F17")),
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Subsignal("data2_n", Pins("F16")),
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Subsignal("scl", Pins("J16")),
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Subsignal("sda", Pins("K16")),
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IOStandard("LVCMOS33")
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),
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("dvi_pots", 0,
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Subsignal("charge", Pins("A18")), # SD_DAT0
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Subsignal("blackout", Pins("C17")), # SD_DAT2
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Subsignal("crossfade", Pins("A17")), # SD_DAT3
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IOStandard("LVCMOS33")
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)
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]
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class Platform(XilinxPlatform):
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identifier = 0x4D31
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default_clk_name = "clk50"
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default_clk_period = 20
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
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def create_programmer(self):
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return UrJTAG(cable="milkymist", flash_proxy_basename="fjmem-m1.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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try:
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eth_clocks = self.lookup_request("eth_clocks")
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self.add_period_constraint(eth_clocks.rx, 40)
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self.add_period_constraint(eth_clocks.tx, 40)
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self.add_platform_command("""
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TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
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TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
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""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
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except ConstraintError:
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pass
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for i in range(2):
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si = "dviclk"+str(i)
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try:
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self.add_period_constraint(self.lookup_request("dvi_in", i).clk, 26.7)
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except ConstraintError:
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pass
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