enjoy-digital 4500641d78 Merge pull request #873 from sthornington/master ... Fix yosys read command for SystemVerilog sources		2021-04-06 12:08:07 +02:00
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build	Fix yosys read command for SystemVerilog sources	2021-04-05 10:37:17 -04:00
compat	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	640x480@60Hz (lowest bandwidth option yet)	2021-04-04 17:20:53 +02:00
tools	tools/litex_json2dts: Fix i2c node	2021-03-28 12:44:45 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00