142 lines
5.1 KiB
Python
142 lines
5.1 KiB
Python
from mibuild.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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_io = [
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("user_led", 0, Pins("Y3")),
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("user_led", 1, Pins("Y1")),
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("user_led", 2, Pins("W2")),
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("user_led", 3, Pins("W1")),
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("user_led", 4, Pins("V3")),
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("user_led", 5, Pins("V1")),
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("user_led", 6, Pins("U2")),
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("user_led", 7, Pins("U1")),
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("clk100", 0,
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Subsignal("p", Pins("B14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("n", Pins("A14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"))
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),
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("gpio", 0, Pins("R8")),
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("gpmc", 0,
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Subsignal("clk", Pins("R26")),
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Subsignal("a", Pins("N17 N18 L23 L24 N19 N20 N21 N22 P17 P19")),
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Subsignal("d", Pins("N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T22 T23 U23 R25")),
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Subsignal("we_n", Pins("W26")),
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Subsignal("oe_n", Pins("AA25")),
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Subsignal("ale_n", Pins("AA26")),
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Subsignal("wait", Pins("AD26")), # WAIT1/BUSY0
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IOStandard("LVCMOS33")),
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# Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side.
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# Numbers here are given on the FPGA side.
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("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0
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("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1
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("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6
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("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2
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("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3
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("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4
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("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5
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# FMC150
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("fmc150_ctrl", 0,
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Subsignal("spi_sclk", Pins("AE5")),
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Subsignal("spi_data", Pins("AF5")),
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Subsignal("adc_sdo", Pins("U13")),
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Subsignal("adc_en_n", Pins("AA15")),
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Subsignal("adc_reset", Pins("V13")),
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Subsignal("cdce_sdo", Pins("AA8")),
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Subsignal("cdce_en_n", Pins("Y9")),
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Subsignal("cdce_reset_n", Pins("AB7")),
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Subsignal("cdce_pd_n", Pins("AC6")),
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Subsignal("cdce_pll_status", Pins("W7")),
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Subsignal("cdce_ref_en", Pins("W8")),
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Subsignal("dac_sdo", Pins("W9")),
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Subsignal("dac_en_n", Pins("W10")),
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Subsignal("mon_sdo", Pins("AC5")),
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Subsignal("mon_en_n", Pins("AD6")),
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Subsignal("mon_reset_n", Pins("AF6")),
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Subsignal("mon_int_n", Pins("AD5")),
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Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33"))
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),
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("ti_dac", 0, # DAC3283
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Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")),
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Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")),
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Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")),
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Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")),
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Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25"))
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),
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("ti_adc", 0, # ADS62P49
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Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")),
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Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")),
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Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")),
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Subsignal("dat_b_n", Pins("AA17 V16 AB19 Y16 AB17 AA16 V15")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
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),
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("fmc150_clocks", 0,
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Subsignal("dac_clk_p", Pins("V12"), IOStandard("LVDS_25")),
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Subsignal("dac_clk_n", Pins("W12"), IOStandard("LVDS_25")),
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Subsignal("adc_clk_p", Pins("AE15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("adc_clk_n", Pins("AF15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("clk_to_fpga", Pins("W24"), IOStandard("LVCMOS25"))
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),
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("fmc150_ext_trigger", 0, Pins("U26")),
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# Vermeer radar testbed
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# Switch controller
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("pca9555", 0,
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Subsignal("sda", Pins("C13")),
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Subsignal("scl", Pins("G8")),
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IOStandard("LVCMOS33")
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),
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# TX path
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("pe43602", 0,
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Subsignal("d", Pins("H8")),
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Subsignal("clk", Pins("B3")),
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Subsignal("le", Pins("F7")),
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IOStandard("LVCMOS33")
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),
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("rfmd2081", 0,
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Subsignal("enx", Pins("E5")),
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Subsignal("sclk", Pins("G6")),
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Subsignal("sdata", Pins("F5")),
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Subsignal("locked", Pins("E6")),
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IOStandard("LVCMOS33")
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),
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# RX path
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("lmh6521", 0,
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Subsignal("scsb", Pins("C5")),
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Subsignal("sclk", Pins("G10")),
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Subsignal("sdi", Pins("D5")),
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Subsignal("sdo", Pins("F9")),
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IOStandard("LVCMOS33")
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),
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("lmh6521", 1,
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Subsignal("scsb", Pins("E10")),
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Subsignal("sclk", Pins("A4")),
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Subsignal("sdi", Pins("B4")),
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Subsignal("sdo", Pins("H10")),
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IOStandard("LVCMOS33")
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),
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("rffc5071", 0,
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Subsignal("enx", Pins("A2")),
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Subsignal("sclk", Pins("G9")),
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Subsignal("sdata", Pins("H9")),
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Subsignal("locked", Pins("A3")),
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IOStandard("LVCMOS33")
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)
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io)
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