152 lines
5.1 KiB
Python
152 lines
5.1 KiB
Python
from mibuild.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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_io = [
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("clk64", 0,
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Subsignal("p", Pins("R7")),
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Subsignal("n", Pins("T7")),
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IOStandard("LVDS_33"),
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Misc("DIFF_TERM=TRUE"),
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),
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("pps", 0, Pins("M14"), Misc("TIG")),
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("reset_n", 0, Pins("D5"), Misc("TIG")),
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("codec_reset", 0, Pins("B14")),
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# recycles fpga_cfg_cclk for reset from fw
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("ext_reset", 0, Pins("R14")),
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("i2c", 0,
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Subsignal("sda", Pins("T13")),
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Subsignal("scl", Pins("R13")),
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),
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("cgen", 0,
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Subsignal("st_ld", Pins("M13")),
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Subsignal("st_refmon", Pins("J14")),
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Subsignal("st_status", Pins("P6")),
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Subsignal("ref_sel", Pins("T2")),
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Subsignal("sync_b", Pins("H15")),
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),
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("fx2_ifclk", 0, Pins("T8")),
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("fx2_gpif", 0,
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Subsignal("d", Pins("P8 P9 N9 T9 R9 P11 P13 N12 "
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"T3 R3 P5 N6 T6 T5 N8 P7")),
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Subsignal("ctl", Pins("M7 M9 M11 P12")),
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Subsignal("slwr", Pins("T4")), # rdy0
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Subsignal("slrd", Pins("R5")), # rdy1
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# Subsignal("rdy2", Pins("T10")),
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# Subsignal("rdy3", Pins("N11")),
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# Subsignal("cs", Pins("P12")),
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Subsignal("sloe", Pins("R11")),
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Subsignal("pktend", Pins("P10")),
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Subsignal("adr", Pins("T11 H16")),
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),
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("user_led", 0, Pins("P4"), Misc("TIG")),
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("user_led", 1, Pins("N4"), Misc("TIG")),
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("user_led", 2, Pins("R2"), Misc("TIG")),
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("debug_clk", 0, Pins("K15 K14")),
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("debug", 0, Pins(
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"K16 J16 C16 C15 E13 D14 D16 D15 "
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"E14 F13 G13 F14 E16 F15 H13 G14 "
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"G16 F16 J12 J13 L14 L16 M15 M16 "
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"L13 K13 P16 N16 R15 P15 N13 N14")),
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("adc", 0,
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Subsignal("sync", Pins("D10")),
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Subsignal("d", Pins("A4 B3 A3 D9 C10 A9 C9 D8 "
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"C8 B8 A8 B15")),
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),
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("dac", 0,
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Subsignal("blank", Pins("K1")),
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Subsignal("sync", Pins("J2")),
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Subsignal("d", Pins("J1 H3 J3 G2 H1 N3 M4 R1 "
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"P2 P1 M1 N1 M3 L4")),
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),
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("codec_spi", 0,
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Subsignal("sclk", Pins("K3")),
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Subsignal("sen", Pins("D13")),
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Subsignal("mosi", Pins("C13")),
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Subsignal("miso", Pins("G4")),
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),
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("aux_spi", 0,
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Subsignal("sen", Pins("C12")),
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Subsignal("sclk", Pins("D12")),
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Subsignal("miso", Pins("J5")),
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),
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("rx_io", 0, Pins("D7 C6 A6 B6 E9 A7 C7 B10 "
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"A10 C11 A11 D11 B12 A12 A14 A13")),
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("tx_io", 0, Pins("K4 L3 L2 F1 F3 G3 E3 E2 "
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"E4 F4 D1 E1 D4 D3 C2 C1")),
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("rx_spi", 0,
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Subsignal("miso", Pins("E6")),
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Subsignal("sen", Pins("B4")),
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Subsignal("mosi", Pins("A5")),
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Subsignal("sclk", Pins("C5")),
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),
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("tx_spi", 0,
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Subsignal("miso", Pins("J4")),
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Subsignal("sen", Pins("N2")),
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Subsignal("mosi", Pins("L1")),
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Subsignal("sclk", Pins("G1")),
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),
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# these are just for information. do not request.
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("mystery_bus", 0, Pins("C4 E7")),
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("fpga_cfg",
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Subsignal("din", Pins("T14")),
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Subsignal("cclk", Pins("R14")),
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Subsignal("init_b", Pins("T12")),
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Subsignal("prog_b", Pins("A2")),
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Subsignal("done", Pins("T15")),
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),
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("jtag",
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Subsignal("tms", Pins("B2")),
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Subsignal("tdo", Pins("B16")),
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Subsignal("tdi", Pins("B1")),
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Subsignal("tck", Pins("A15")),
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),
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk64"
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default_clk_period = 15.625
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def __init__(self):
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XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
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self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_platform_command("""
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TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
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""")
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try:
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ifclk = self.lookup_request("fx2_ifclk")
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gpif = self.lookup_request("fx2_gpif")
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for i, d in [(gpif.d, "in"), (gpif.d, "out"),
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(gpif.ctl, "in"), (gpif.adr, "out"),
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(gpif.slwr, "out"), (gpif.sloe, "out"),
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(gpif.slrd, "out"), (gpif.pktend, "out")]:
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if flen(i) > 1:
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q = "(*)"
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else:
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q = ""
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self.add_platform_command("""
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INST "{i}%s" TNM = gpif_net_%s;
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""" % (q, d), i=i)
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self.add_platform_command("""
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NET "{ifclk}" TNM_NET = "GRPifclk";
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TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%;
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TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING;
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TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING;
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""", ifclk=ifclk)
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except ConstraintError:
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pass
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