73 lines
3.0 KiB
Python
73 lines
3.0 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.interconnect import wishbone, avalon
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# TestWishbone -------------------------------------------------------------------------------------
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class TestAvalon2Wishbone(unittest.TestCase):
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def test_sram(self):
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def generator(dut):
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yield from dut.avl.bus_write(0x0000, 0x01234567)
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yield from dut.avl.bus_write(0x0004, 0x89abcdef)
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yield from dut.avl.bus_write(0x0008, 0xdeadbeef)
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yield from dut.avl.bus_write(0x000c, 0xc0ffee00)
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yield from dut.avl.bus_write(0x0010, 0x76543210)
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yield
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self.assertEqual((yield from dut.avl.bus_read(0x0000)), 0x01234567)
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self.assertEqual((yield from dut.avl.bus_read(0x0004)), 0x89abcdef)
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self.assertEqual((yield from dut.avl.bus_read(0x0008)), 0xdeadbeef)
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self.assertEqual((yield from dut.avl.bus_read(0x000c)), 0xc0ffee00)
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self.assertEqual((yield from dut.avl.bus_read(0x0010)), 0x76543210)
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class DUT(Module):
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def __init__(self):
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a2w = avalon.AvalonMM2Wishbone()
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self.avl = a2w.a2w_avl
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wishbone_mem = wishbone.SRAM(32, bus=a2w.a2w_wb)
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self.submodules += a2w
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut)) #, vcd_name="avalon.vcd")
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def test_sram_burst(self):
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def generator(dut):
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yield from dut.avl.bus_write(0x0, [0x01234567, 0x89abcdef, 0xdeadbeef, 0xc0ffee00, 0x76543210])
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yield
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self.assertEqual((yield from dut.avl.bus_read(0x0000, burstcount=5)), 0x01234567)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0x89abcdef)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0xdeadbeef)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0xc0ffee00)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0x76543210)
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yield
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yield
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yield
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yield
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self.assertEqual((yield from dut.avl.bus_read(0x0000)), 0x01234567)
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self.assertEqual((yield from dut.avl.bus_read(0x0004)), 0x89abcdef)
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self.assertEqual((yield from dut.avl.bus_read(0x0008)), 0xdeadbeef)
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self.assertEqual((yield from dut.avl.bus_read(0x000c)), 0xc0ffee00)
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self.assertEqual((yield from dut.avl.bus_read(0x0010)), 0x76543210)
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yield
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yield
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class DUT(Module):
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def __init__(self):
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a2w = avalon.AvalonMM2Wishbone()
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self.avl = a2w.a2w_avl
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wishbone_mem = wishbone.SRAM(32, bus=a2w.a2w_wb)
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self.submodules += a2w
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut)) #, vcd_name="avalon_burst.vcd")
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