106 lines
3.6 KiB
Python
106 lines
3.6 KiB
Python
from migen.genlib.io import DDROutput
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from migen.flow.plumbing import Multiplexer, Demultiplexer
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from migen.genlib.cdc import MultiReg
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.generic import *
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from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG
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from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
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from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
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modes = {
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"GMII": 0,
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"MII": 1
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}
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tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
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rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
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class LiteEthPHYGMIIMIITX(Module):
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def __init__(self, pads, mode):
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self.sink = sink = Sink(eth_phy_description(8))
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###
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gmii_tx_pads = Record(tx_pads_layout)
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gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
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self.submodules += gmii_tx
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mii_tx_pads = Record(tx_pads_layout)
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mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
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self.submodules += mii_tx
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demux = Demultiplexer(eth_phy_description(8), 2)
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self.submodules += demux
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self.comb += [
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demux.sel.eq(mode == modes["MII"]),
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Record.connect(sink, demux.sink),
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Record.connect(demux.source0, gmii_tx.sink),
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Record.connect(demux.source1, mii_tx.sink),
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]
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if hasattr(pads, "tx_er"):
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self.comb += pads.tx_er.eq(0)
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self.sync += [
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If(mode == modes["MII"],
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pads.tx_en.eq(mii_tx_pads.tx_en),
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pads.tx_data.eq(mii_tx_pads.tx_data),
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).Else(
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pads.tx_en.eq(gmii_tx_pads.tx_en),
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pads.tx_data.eq(gmii_tx_pads.tx_data),
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)
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]
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class LiteEthPHYGMIIMIIRX(Module):
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def __init__(self, pads, mode):
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self.source = source = Source(eth_phy_description(8))
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###
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pads_d = Record(rx_pads_layout)
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self.sync += [
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pads_d.dv.eq(pads.dv),
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pads_d.rx_data.eq(pads.rx_data)
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]
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gmii_rx = LiteEthPHYGMIIRX(pads_d)
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self.submodules += gmii_rx
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mii_rx = LiteEthPHYMIIRX(pads_d)
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self.submodules += mii_rx
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mux = Multiplexer(eth_phy_description(8), 2)
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self.submodules += mux
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self.comb += [
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mux.sel.eq(mode == modes["MII"]),
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Record.connect(gmii_rx.source, mux.sink0),
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Record.connect(mii_rx.source, mux.sink1),
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Record.connect(mux.source, source)
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]
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class LiteEthGMIIMIIClockCounter(Module, AutoCSR):
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def __init__(self):
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self._reset = CSRStorage()
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self._value = CSRStatus(32)
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###
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counter = RenameClockDomains(Counter(32), "eth_rx")
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self.submodules += counter
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self.comb += [
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counter.reset.eq(self._reset.storage), # slow, don't need CDC
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counter.ce.eq(1),
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]
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self.specials += MultiReg(counter.value, self._value.status)
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class LiteEthPHYGMIIMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self._mode = CSRStorage()
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mode = self._mode.storage
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# Note: we can use GMII CRG since it also handles tx clock pad used for MII
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
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self.submodules.clock_counter = LiteEthGMIIMIIClockCounter()
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self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
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self.sink, self.source = self.tx.sink, self.rx.source
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