litex/misoclib/soc
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
2015-03-21 12:55:39 +01:00
..
__init__.py soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
cpuif.py cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
sdram.py sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 2015-03-21 12:55:39 +01:00