enjoy-digital 4608bd1864 Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings ... litex_sim: add option to create SDRAM module from SPD data		2020-04-25 08:27:00 +02:00
..
boards	platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.	2020-04-18 11:38:24 +02:00
build	build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).	2020-04-22 12:01:23 +02:00
gen	litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.	2020-04-10 08:47:07 +02:00
soc	soc/cores/spi: add optional aligned mode.	2020-04-22 13:15:51 +02:00
tools	Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings	2020-04-25 08:27:00 +02:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00