litex/migen
Sebastien Bourdeauducq 46b1f74e98 bus/asmibus/hub: forward data and tag_call 2012-02-14 14:00:17 +01:00
..
actorlib Use enumerate(x) instead of zip(range(x), x) 2012-02-02 21:28:00 +01:00
bank Use double quotes for all strings 2012-02-14 13:12:43 +01:00
bus bus/asmibus/hub: forward data and tag_call 2012-02-14 14:00:17 +01:00
corelogic Use double quotes for all strings 2012-02-14 13:12:43 +01:00
fhdl fhdl: do not attempt slicing non-array signals to keep Verilog happy 2012-02-06 18:07:02 +01:00
flow Use double quotes for all strings 2012-02-14 13:12:43 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00