152 lines
4.4 KiB
Python
152 lines
4.4 KiB
Python
from migen import *
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from migen.genlib.record import *
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from migen.genlib import fifo
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def _make_m2s(layout):
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r = []
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for f in layout:
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if isinstance(f[1], (int, tuple)):
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r.append((f[0], f[1], DIR_M_TO_S))
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else:
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r.append((f[0], _make_m2s(f[1])))
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return r
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class EndpointDescription:
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def __init__(self, payload_layout, packetized=False):
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self.payload_layout = payload_layout
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self.packetized = packetized
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def get_full_layout(self):
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reserved = {"stb", "ack", "payload", "sop", "eop", "description"}
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attributed = set()
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for f in self.payload_layout:
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if f[0] in attributed:
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raise ValueError(f[0] + " already attributed in payload layout")
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if f[0] in reserved:
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raise ValueError(f[0] + " cannot be used in endpoint layout")
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attributed.add(f[0])
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full_layout = [
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("payload", _make_m2s(self.payload_layout)),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M)
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]
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if self.packetized:
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full_layout += [
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("sop", 1, DIR_M_TO_S),
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("eop", 1, DIR_M_TO_S)
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]
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return full_layout
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class _Endpoint(Record):
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def __init__(self, description_or_layout):
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if isinstance(description_or_layout, EndpointDescription):
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self.description = description_or_layout
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else:
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self.description = EndpointDescription(description_or_layout)
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Record.__init__(self, self.description.get_full_layout())
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def __getattr__(self, name):
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return getattr(object.__getattribute__(self, "payload"), name)
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class Source(_Endpoint):
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def connect(self, sink):
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return Record.connect(self, sink)
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class Sink(_Endpoint):
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def connect(self, source):
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return source.connect(self)
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class _FIFOWrapper(Module):
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def __init__(self, fifo_class, layout, depth):
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self.sink = Sink(layout)
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self.source = Source(layout)
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self.busy = Signal()
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###
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description = self.sink.description
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fifo_layout = [("payload", description.payload_layout)]
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if description.packetized:
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fifo_layout += [("sop", 1), ("eop", 1)]
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self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
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fifo_in = Record(fifo_layout)
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fifo_out = Record(fifo_layout)
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self.comb += [
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self.fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(self.fifo.dout)
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]
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self.comb += [
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self.sink.ack.eq(self.fifo.writable),
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self.fifo.we.eq(self.sink.stb),
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fifo_in.payload.eq(self.sink.payload),
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self.source.stb.eq(self.fifo.readable),
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self.source.payload.eq(fifo_out.payload),
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self.fifo.re.eq(self.source.ack)
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]
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if description.packetized:
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self.comb += [
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fifo_in.sop.eq(self.sink.sop),
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fifo_in.eop.eq(self.sink.eop),
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self.source.sop.eq(fifo_out.sop),
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self.source.eop.eq(fifo_out.eop)
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]
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class SyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth, buffered=False):
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_FIFOWrapper.__init__(
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self,
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fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
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layout, depth)
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class AsyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth):
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_FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)
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class Multiplexer(Module):
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def __init__(self, layout, n):
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self.source = Source(layout)
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sinks = []
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for i in range(n):
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sink = Sink(layout)
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setattr(self, "sink"+str(i), sink)
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sinks.append(sink)
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self.sel = Signal(max=n)
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# # #
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cases = {}
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for i, sink in enumerate(sinks):
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cases[i] = Record.connect(sink, self.source)
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self.comb += Case(self.sel, cases)
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class Demultiplexer(Module):
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def __init__(self, layout, n):
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self.sink = Sink(layout)
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sources = []
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for i in range(n):
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source = Source(layout)
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setattr(self, "source"+str(i), source)
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sources.append(source)
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self.sel = Signal(max=n)
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# # #
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cases = {}
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for i, source in enumerate(sources):
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cases[i] = Record.connect(self.sink, source)
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self.comb += Case(self.sel, cases)
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