Robert Jordens 47ea451315 pipistrello: compress and load bitstream at 6MHz		2015-03-19 18:48:45 +01:00
..
altera	mibuild/altera: use new Toolchain/Platform architecture	2015-03-16 21:07:55 +01:00
lattice	mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)	2015-03-18 18:54:22 +01:00
platforms	pipistrello: compress and load bitstream at 6MHz	2015-03-19 18:48:45 +01:00
sim	mibuild/sim: clean up (thanks sb)	2015-03-10 16:41:52 +01:00
xilinx	mibuild/xilinx/common: add XilinxDDROutput	2015-03-16 22:53:05 +01:00
__init__.py
generic_platform.py	fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"	2015-03-18 14:59:22 +01:00
generic_programmer.py
tools.py