This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litex
mirror of
https://github.com/enjoy-digital/litex.git
Watch
1
Star
0
Fork
You've already forked litex
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
48ddbf0c85
litex
/
verilog
History
Sebastien Bourdeauducq
cdd58e023b
s6ddrphy: use single-ended DQS
2012-02-17 10:53:58 +01:00
..
lm32
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
m1crg
Generate all clocks for the DDR PHY
2012-02-16 18:02:37 +01:00
s6ddrphy
s6ddrphy: use single-ended DQS
2012-02-17 10:53:58 +01:00