Florent Kermarrec 48e5a1d140 soc/cores: uniformize (continue)		2019-09-29 17:04:21 +02:00
..
cores	soc/cores: uniformize (continue)	2019-09-29 17:04:21 +02:00
integration	soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)	2019-09-29 15:47:10 +02:00
interconnect	wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)	2019-09-24 17:55:29 +02:00
software	software/libbase/uart: add polling mode	2019-09-28 00:35:26 +02:00
__init__.py