litex/litex/soc
2020-07-20 13:48:49 +02:00
..
cores soc/cores/spi/SPIMaster: rewrite/simplify. 2020-07-20 10:44:18 +02:00
doc soc/doc/csr: allow CSRField.reset to be a Migen Constant. 2020-03-23 18:47:41 +01:00
integration spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. 2020-07-17 11:58:26 +02:00
interconnect soc/interconnect/axi: propagate response errors in AXILiteDownConverter 2020-07-16 17:16:35 +02:00
software software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. 2020-07-20 13:48:49 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00