129 lines
4.1 KiB
Python
129 lines
4.1 KiB
Python
from operator import itemgetter
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from collections import defaultdict
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from math import ceil
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from migen.fhdl.std import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr, lasmibus, dfi
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from migen.bus import wishbone2lasmi, wishbone2csr
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from misoclib import lm32, uart, dfii, lasmicon, identifier, timer, memtest
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class GenSoC(Module):
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csr_base = 0xe0000000
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csr_map = {
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"crg": 0, # user
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"uart": 1, # provided
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"identifier": 2, # provided
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"timer0": 3, # provided
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"buttons": 4, # user
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"leds": 5, # user
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}
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interrupt_map = {
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"uart": 0,
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"timer0": 1,
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}
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known_platform_id = defaultdict(lambda: 0x554E, {
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"mixxeo": 0x4D58,
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"m1": 0x4D31
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})
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def __init__(self, platform, clk_freq, sram_size, l2_size=0):
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self.clk_freq = clk_freq
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self.sram_size = sram_size
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self.l2_size = l2_size
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# Wishbone
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self.submodules.cpu = lm32.LM32()
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self.submodules.sram = wishbone.SRAM(sram_size)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
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# rom 0x00000000 (shadow @0x80000000) user
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# SRAM/debug 0x10000000 (shadow @0x90000000) provided
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# CSR bridge 0x60000000 (shadow @0xe0000000) provided
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self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
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self._wb_slaves = [
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(lambda a: a[26:29] == 1, self.sram.bus),
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(lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
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]
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# CSR
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq),
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log2_int(l2_size) if l2_size else 0)
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self.submodules.timer0 = timer.Timer()
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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# Interrupts
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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if margin:
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t += clk_period_ns/2
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return ceil(t/clk_period_ns)
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class SDRAMSoC(GenSoC):
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csr_map = {
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"dfii": 6,
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"lasmicon": 7,
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"memtest_w": 8,
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"memtest_r": 9
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}
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csr_map.update(GenSoC.csr_map)
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def __init__(self, platform, clk_freq, sram_size, l2_size, with_memtest):
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GenSoC.__init__(self, platform, clk_freq, sram_size, l2_size)
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self.with_memtest = with_memtest
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self._sdram_modules_created = False
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def create_sdram_modules(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):
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if self._sdram_modules_created:
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raise FinalizeError
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self._sdram_modules_created = True
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# DFI
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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phy_settings.dfi_d, phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi)
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# LASMI
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self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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if self.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())
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# Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
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self.add_wb_slave(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone)
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def do_finalize(self):
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if not self._sdram_modules_created:
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raise FinalizeError("Need to call SDRAMSoC.create_sdram_modules()")
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GenSoC.do_finalize(self)
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