Florent Kermarrec 4aa07f2ae9 soc/interconnect: rename axi to axi_lite		2019-02-27 22:11:09 +01:00
..
cores	soc/cores/clock: add actual clk_freqs to config	2019-02-14 10:41:27 +01:00
integration	soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches	2019-02-12 12:12:40 +01:00
interconnect	soc/interconnect: rename axi to axi_lite	2019-02-27 22:11:09 +01:00
software	soc/software/sdram: fix compilation on ultrascale	2019-02-25 16:12:21 +01:00
tools	soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write	2019-02-16 00:08:24 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00