191 lines
4.0 KiB
Verilog
191 lines
4.0 KiB
Verilog
module s6ddrphy #(
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parameter NUM_AD = 0,
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parameter NUM_BA = 0,
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parameter NUM_D = 0 /* < number of data lines per DFI phase */
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) (
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/* Clocks */
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input sys_clk,
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input clk2x_90,
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input clk4x_wr,
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input clk4x_wr_strb,
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input clk4x_rd,
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input clk4x_rd_strb,
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/* DFI phase 0 */
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input [NUM_AD-1:0] dfi_address_p0,
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input [NUM_BA-1:0] dfi_bank_p0,
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input dfi_cs_n_p0,
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input dfi_cke_p0,
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input dfi_ras_n_p0,
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input dfi_cas_n_p0,
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input dfi_we_n_p0,
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input dfi_wrdata_en_p0,
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input [NUM_D/8-1:0] dfi_wrdata_mask_p0,
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input [NUM_D-1:0] dfi_wrdata_p0,
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input dfi_rddata_en_p0,
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output [NUM_D-1:0] dfi_rddata_w0,
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output dfi_rddata_valid_w0,
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/* DFI phase 1 */
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input [NUM_AD-1:0] dfi_address_p1,
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input [NUM_BA-1:0] dfi_bank_p1,
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input dfi_cs_n_p1,
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input dfi_cke_p1,
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input dfi_ras_n_p1,
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input dfi_cas_n_p1,
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input dfi_we_n_p1,
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input dfi_wrdata_en_p1,
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input [NUM_D/8-1:0] dfi_wrdata_mask_p1,
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input [NUM_D-1:0] dfi_wrdata_p1,
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input dfi_rddata_en_p1,
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output [NUM_D-1:0] dfi_rddata_w1,
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output dfi_rddata_valid_w1,
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/* DDR SDRAM pads */
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output sd_clk_out_p,
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output sd_clk_out_n,
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output reg [NUM_AD-1:0] sd_a,
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output reg [NUM_BA-1:0] sd_ba,
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output reg sd_cs_n,
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output reg sd_cke,
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output reg sd_ras_n,
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output reg sd_cas_n,
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output reg sd_we_n,
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inout [NUM_D/2-1:0] sd_dq,
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output [NUM_D/16-1:0] sd_dm,
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inout [NUM_D/16-1:0] sd_dqs
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);
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/*
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* SDRAM clock
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*/
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) sd_clk_forward_p (
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.Q(sd_clk_out_p),
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.C0(clk2x_90),
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.C1(~clk2x_90),
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.CE(1'b1),
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.D0(1'b1),
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.D1(1'b0),
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.R(1'b0),
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.S(1'b0)
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);
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) sd_clk_forward_n (
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.Q(sd_clk_out_n),
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.C0(clk2x_90),
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.C1(~clk2x_90),
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.CE(1'b1),
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.D0(1'b0),
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.D1(1'b1),
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.R(1'b0),
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.S(1'b0)
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);
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/*
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* Command/address
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*/
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reg phase_sel;
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always @(negedge clk2x_90)
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phase_sel <= sys_clk;
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reg [NUM_AD-1:0] r_dfi_address_p0;
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reg [NUM_BA-1:0] r_dfi_bank_p0;
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reg r_dfi_cs_n_p0;
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reg r_dfi_cke_p0;
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reg r_dfi_ras_n_p0;
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reg r_dfi_cas_n_p0;
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reg r_dfi_we_n_p0;
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reg [NUM_AD-1:0] r_dfi_address_p1;
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reg [NUM_BA-1:0] r_dfi_bank_p1;
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reg r_dfi_cs_n_p1;
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reg r_dfi_cke_p1;
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reg r_dfi_ras_n_p1;
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reg r_dfi_cas_n_p1;
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reg r_dfi_we_n_p1;
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always @(posedge sys_clk) begin
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r_dfi_address_p0 <= dfi_address_p0;
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r_dfi_bank_p0 <= dfi_bank_p0;
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r_dfi_cs_n_p0 <= dfi_cs_n_p0;
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r_dfi_cke_p0 <= dfi_cke_p0;
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r_dfi_ras_n_p0 <= dfi_ras_n_p0;
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r_dfi_cas_n_p0 <= dfi_cas_n_p0;
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r_dfi_we_n_p0 <= dfi_we_n_p0;
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r_dfi_address_p1 <= dfi_address_p1;
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r_dfi_bank_p1 <= dfi_bank_p1;
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r_dfi_cs_n_p1 <= dfi_cs_n_p1;
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r_dfi_cke_p1 <= dfi_cke_p1;
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r_dfi_ras_n_p1 <= dfi_ras_n_p1;
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r_dfi_cas_n_p1 <= dfi_cas_n_p1;
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r_dfi_we_n_p1 <= dfi_we_n_p1;
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end
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reg [NUM_AD-1:0] r2_dfi_address_p0;
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reg [NUM_BA-1:0] r2_dfi_bank_p0;
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reg r2_dfi_cs_n_p0;
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reg r2_dfi_cke_p0;
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reg r2_dfi_ras_n_p0;
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reg r2_dfi_cas_n_p0;
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reg r2_dfi_we_n_p0;
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reg [NUM_AD-1:0] r2_dfi_address_p1;
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reg [NUM_BA-1:0] r2_dfi_bank_p1;
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reg r2_dfi_cs_n_p1;
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reg r2_dfi_cke_p1;
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reg r2_dfi_ras_n_p1;
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reg r2_dfi_cas_n_p1;
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reg r2_dfi_we_n_p1;
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always @(negedge clk2x_90) begin
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r2_dfi_address_p0 <= r_dfi_address_p0;
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r2_dfi_bank_p0 <= r_dfi_bank_p0;
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r2_dfi_cs_n_p0 <= r_dfi_cs_n_p0;
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r2_dfi_cke_p0 <= r_dfi_cke_p0;
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r2_dfi_ras_n_p0 <= r_dfi_ras_n_p0;
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r2_dfi_cas_n_p0 <= r_dfi_cas_n_p0;
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r2_dfi_we_n_p0 <= r_dfi_we_n_p0;
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r2_dfi_address_p1 <= r_dfi_address_p1;
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r2_dfi_bank_p1 <= r_dfi_bank_p1;
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r2_dfi_cs_n_p1 <= r_dfi_cs_n_p1;
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r2_dfi_cke_p1 <= r_dfi_cke_p1;
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r2_dfi_ras_n_p1 <= r_dfi_ras_n_p1;
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r2_dfi_cas_n_p1 <= r_dfi_cas_n_p1;
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r2_dfi_we_n_p1 <= r_dfi_we_n_p1;
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end
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always @(posedge clk2x_90) begin
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if(phase_sel) begin
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sd_a <= r2_dfi_address_p1;
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sd_ba <= r2_dfi_bank_p1;
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sd_cs_n <= r2_dfi_cs_n_p1;
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sd_cke <= r2_dfi_cke_p1;
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sd_ras_n <= r2_dfi_ras_n_p1;
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sd_cas_n <= r2_dfi_cas_n_p1;
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sd_we_n <= r2_dfi_we_n_p1;
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end else begin
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sd_a <= r2_dfi_address_p0;
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sd_ba <= r2_dfi_bank_p0;
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sd_cs_n <= r2_dfi_cs_n_p0;
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sd_cke <= r2_dfi_cke_p0;
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sd_ras_n <= r2_dfi_ras_n_p0;
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sd_cas_n <= r2_dfi_cas_n_p0;
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sd_we_n <= r2_dfi_we_n_p0;
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end
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end
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// TODO
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assign sd_dq = 32'hzzzzzzzz;
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assign sd_dm = 0;
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assign sd_dqs = 4'hz;
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endmodule
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