16 lines
454 B
Python
16 lines
454 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl import verilog
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from migen.genlib.fsm import FSM
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class Example(Module):
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def __init__(self):
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self.s = Signal()
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myfsm = FSM("FOO", "BAR")
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self.submodules += myfsm
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myfsm.act(myfsm.FOO, self.s.eq(1), myfsm.next_state(myfsm.BAR))
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myfsm.act(myfsm.BAR, self.s.eq(0), myfsm.next_state(myfsm.FOO))
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example = Example()
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print(verilog.convert(example, {example.s}))
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