32 lines
851 B
Python
32 lines
851 B
Python
from migen.fhdl.std import *
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from migen.flow.actor import Sink, Source
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from migen.bank.description import *
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from migen.genlib.record import *
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from liteethernet.common import *
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class LoopbackPHYCRG(Module, AutoCSR):
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def __init__(self):
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self._reset = CSRStorage()
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###
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal())
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]
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reset = self._reset.storage
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self.comb += [
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self.cd_eth_rx.rst.eq(reset),
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self.cd_eth_tx.rst.eq(reset)
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]
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class LoopbackPHY(Module, AutoCSR):
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def __init__(self):
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self.dw = 8
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self.submodules.crg = LoopbackPHYCRG()
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self.sink = sink = Sink(eth_description(8))
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self.source = source = Source(eth_description(8))
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self.comb += Record.connect(self.sink, self.source)
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