245 lines
7.2 KiB
Python
245 lines
7.2 KiB
Python
from copy import copy
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import os, argparse
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from migen.fhdl.structure import *
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from migen.genlib.record import Record
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from migen.fhdl import verilog
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from mibuild import tools
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class ConstraintError(Exception):
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pass
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class Pins:
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def __init__(self, *identifiers):
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self.identifiers = identifiers
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class IOStandard:
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def __init__(self, name):
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self.name = name
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class Drive:
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def __init__(self, strength):
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self.strength = strength
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class Misc:
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def __init__(self, misc):
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self.misc = misc
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class Subsignal:
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def __init__(self, name, *constraints):
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self.name = name
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self.constraints = list(constraints)
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def _lookup(description, name, number):
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for resource in description:
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if resource[0] == name and (number is None or resource[1] == number):
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return resource
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raise ConstraintError("Resource not found: " + name + ":" + str(number))
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def _resource_type(resource, name_map):
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t = None
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for element in resource[2:]:
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if isinstance(element, Pins):
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assert(t is None)
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t = len(element.identifiers)
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elif isinstance(element, Subsignal):
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if t is None:
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t = []
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assert(isinstance(t, list))
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n_bits = None
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for c in element.constraints:
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if isinstance(c, Pins):
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assert(n_bits is None)
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n_bits = len(c.identifiers)
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t.append((name_map(element.name), n_bits))
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return t
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def _match(description, requests):
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available = list(description)
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matched = []
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# 1. Match requests for a specific number
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for request in requests:
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if request[1] is not None:
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resource = _lookup(available, request[0], request[1])
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available.remove(resource)
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matched.append((resource, request[2], request[3]))
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# 2. Match requests for no specific number
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for request in requests:
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if request[1] is None:
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resource = _lookup(available, request[0], request[1])
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available.remove(resource)
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matched.append((resource, request[2], request[3]))
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return matched
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def _separate_pins(constraints):
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pins = None
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others = []
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for c in constraints:
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if isinstance(c, Pins):
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assert(pins is None)
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pins = c.identifiers
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else:
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others.append(c)
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return pins, others
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class ConstraintManager:
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def __init__(self, description):
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self.description = description
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self.requests = []
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self.platform_commands = []
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self.io_signals = set()
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def request(self, name, number=None, obj=None, name_map=lambda s: s):
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r = _lookup(self.description, name, number)
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t = _resource_type(r, name_map)
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# If obj is None, then create it.
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# If it already exists, do some sanity checking.
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# Update io_signals at the same time.
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if obj is None:
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if isinstance(t, int):
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obj = Signal(t, name_override=name_map(r[0]))
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self.io_signals.add(obj)
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else:
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obj = Record(t, name=r[0])
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for sig in obj.flatten():
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self.io_signals.add(sig)
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else:
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if isinstance(t, int):
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assert(isinstance(obj, Signal) and obj.nbits == t)
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self.io_signals.add(obj)
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else:
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for attr, nbits in t:
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sig = getattr(obj, attr)
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assert(isinstance(sig, Signal) and sig.nbits == nbits)
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self.io_signals.add(sig)
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# Register the request
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self.requests.append((name, number, obj, name_map))
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return obj
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def add_platform_command(self, command, **signals):
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self.platform_commands.append((command, signals))
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def get_io_signals(self):
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return self.io_signals
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def get_sig_constraints(self):
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r = []
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matched = _match(self.description, self.requests)
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for resource, obj, name_map in matched:
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name = resource[0]
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number = resource[1]
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has_subsignals = False
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top_constraints = []
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for element in resource[2:]:
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if isinstance(element, Subsignal):
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has_subsignals = True
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else:
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top_constraints.append(element)
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if has_subsignals:
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for element in resource[2:]:
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if isinstance(element, Subsignal):
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sig = getattr(obj, name_map(element.name))
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pins, others = _separate_pins(top_constraints + element.constraints)
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r.append((sig, pins, others, (name, number, element.name)))
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else:
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pins, others = _separate_pins(top_constraints)
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r.append((obj, pins, others, (name, number, None)))
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return r
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def get_platform_commands(self):
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return self.platform_commands
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def save(self):
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return copy(self.requests), copy(self.platform_commands), copy(self.io_signals)
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def restore(self, backup):
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self.request, self.platform_commands, self.io_signals = backup
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class GenericPlatform:
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def __init__(self, device, io, default_crg_factory=None, name=None):
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self.device = device
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self.constraint_manager = ConstraintManager(io)
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self.default_crg_factory = default_crg_factory
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if name is None:
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name = self.__module__.split(".")[-1]
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self.name = name
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self.sources = []
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def request(self, *args, **kwargs):
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return self.constraint_manager.request(*args, **kwargs)
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def add_platform_command(self, *args, **kwargs):
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return self.constraint_manager.add_platform_command(*args, **kwargs)
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def add_source(self, filename, language=None):
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if language is None:
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language = tools.language_by_filename(filename)
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if language is None:
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language = "verilog" # default to Verilog
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filename = os.path.abspath(filename)
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self.sources.append((filename, language))
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def add_sources(self, path, *filenames, language=None):
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for f in filenames:
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self.add_source(os.path.join(path, f), language)
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def add_source_dir(self, path):
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for root, dirs, files in os.walk(path):
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for filename in files:
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language = tools.language_by_filename(filename)
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if language is not None:
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self.add_source(os.path.join(root, filename), language)
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def get_verilog(self, fragment, clock_domains=None, **kwargs):
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# We may create a temporary clock/reset generator that would request pins.
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# Save the constraint manager state so that such pin requests disappear
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# at the end of this function.
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backup = self.constraint_manager.save()
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try:
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# if none exists, create a default clock domain and drive it
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if clock_domains is None:
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if self.default_crg_factory is None:
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raise NotImplementedError("No clock/reset generator defined by either platform or user")
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crg = self.default_crg_factory(self)
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frag = fragment + crg.get_fragment()
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clock_domains = crg.get_clock_domains()
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else:
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frag = fragment
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# generate Verilog
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src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
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clock_domains=clock_domains, return_ns=True, **kwargs)
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# resolve signal names in constraints
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sc = self.constraint_manager.get_sig_constraints()
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named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
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# resolve signal names in platform commands
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pc = self.constraint_manager.get_platform_commands()
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named_pc = []
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for template, args in pc:
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name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items())
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named_pc.append(template.format(**name_dict))
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finally:
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self.constraint_manager.restore(backup)
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return src, named_sc, named_pc
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def build(self, fragment, clock_domains=None):
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raise NotImplementedError("GenericPlatform.build must be overloaded")
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def add_arguments(self, parser):
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pass # default: no arguments
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def build_arg_ns(self, ns, *args, **kwargs):
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self.build(*args, **kwargs)
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def build_cmdline(self, *args, **kwargs):
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parser = argparse.ArgumentParser(description="FPGA bitstream build system")
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self.add_arguments(parser)
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ns = parser.parse_args()
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self.build_arg_ns(ns, *args, **kwargs)
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