litex/litex
2021-01-25 12:29:18 +01:00
..
build build/tools/language_by_filename: add svo to system-verilog extensions. 2021-01-18 16:29:52 +01:00
gen gen/fhdl/verilog: improve clock domain error reporting. 2020-11-10 13:27:29 +01:00
soc cores/uart: expose fsm/timer (to ease probing with LiteScope). 2021-01-25 12:29:18 +01:00
tools tools/litex_server: add initial JTAG-UART support. 2021-01-22 14:19:38 +01:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00