Florent Kermarrec c120f6d457 build/openocd: add set_qe parameter to flash ... QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.		2019-09-12 17:07:56 +02:00
..
altera	build/altera/quartus: add add_ip method to use Quartus QSYS files	2019-08-15 13:45:29 +02:00
lattice	gen/fhdl/verilog: allow single element verilog inline attribute	2019-08-28 05:24:11 +02:00
microsemi	libero enable enhanced constraints	2019-08-16 10:31:53 +02:00
sim	software/bios: switch to standard CRLF	2019-08-27 09:45:44 +02:00
xilinx	build/xilinx/vivado: use "" for strings	2019-08-14 19:03:10 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
generic_platform.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
generic_programmer.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
openocd.py	build/openocd: add set_qe parameter to flash	2019-09-12 17:07:56 +02:00
tools.py	Only write file if contents will change.	2019-09-02 14:26:41 -07:00