70 lines
1.7 KiB
Python
70 lines
1.7 KiB
Python
from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.actorlib.sim import Dumper
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.genlib.ioo import UnifiedIOSimulation
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from migen.pytholite.transel import Register
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from migen.pytholite.compiler import Pytholite
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from migen.sim.generic import Simulator
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from migen.fhdl.std import *
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from migen.fhdl import verilog
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layout = [("r", 32)]
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def gen():
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ds = Register(32)
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for i in range(3):
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r = TRead(i, busname="mem")
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yield r
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ds.store = r.data
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yield Token("result", {"r": ds})
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for i in range(5):
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r = TRead(i, busname="wb")
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yield r
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ds.store = r.data
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yield Token("result", {"r": ds})
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class SlaveModel(wishbone.TargetModel):
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def read(self, address):
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return address + 4
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class TestBench(Module):
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def __init__(self, ng):
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g = DataFlowGraph()
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d = Dumper(layout)
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g.add_connection(ng, d)
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self.submodules.slave = wishbone.Target(SlaveModel())
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self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.wb, self.slave.bus)
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self.submodules.ca = CompositeActor(g)
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def run_sim(ng):
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sim = Simulator(TestBench(ng))
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sim.run(50)
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del sim
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def add_interfaces(obj):
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obj.result = Source(layout)
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obj.wb = wishbone.Interface()
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obj.mem = Memory(32, 3, init=[42, 37, 81])
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obj.finalize()
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def main():
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print("Simulating native Python:")
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ng_native = UnifiedIOSimulation(gen())
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add_interfaces(ng_native)
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run_sim(ng_native)
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print("Simulating Pytholite:")
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ng_pytholite = Pytholite(gen)
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add_interfaces(ng_pytholite)
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run_sim(ng_pytholite)
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print("Converting Pytholite to Verilog:")
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ng_pytholite = Pytholite(gen)
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add_interfaces(ng_pytholite)
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print(verilog.convert(ng_pytholite))
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main()
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