Florent Kermarrec 4f15be746c tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter. ... Fix jtag_uart regression and allow serialboot.		2021-02-05 09:40:21 +01:00
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build	Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow	2021-02-04 16:41:45 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	doc: Fix doc build with Sphinx v1.x	2021-02-04 09:40:04 +01:00
tools	tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter.	2021-02-05 09:40:21 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00