Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
litex/litex/soc
History
Tim 'mithro' Ansell 4f565c5179 stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
..
cores cores/clock/S7: just reset the generated clock, not the PLL/MMCM 2018-11-13 14:47:04 +01:00
integration soc_core: check for cpu before checking interrupt 2018-11-13 16:17:49 +01:00
interconnect stream.Endpoint: Pass extra arguments to superclass. 2018-11-25 12:57:11 -08:00
software bios/main: fix typo on mor1kx 2018-11-13 11:16:06 +01:00
tools litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
MISOC_LICENSE litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00