86 lines
2.4 KiB
Python
86 lines
2.4 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.fhdl.specials import Memory
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migen.actorlib.fifo import SyncFIFO
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class Recorder(Module, AutoCSR):
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def __init__(self, width, depth):
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self.width = width
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self.sink = Sink([("hit", 1), ("d", width)])
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self._r_trigger = CSR()
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self._r_length = CSRStorage(bits_for(depth))
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self._r_offset = CSRStorage(bits_for(depth))
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self._r_done = CSRStatus()
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self._r_read_en = CSR()
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self._r_read_empty = CSRStatus()
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self._r_read_dat = CSRStatus(width)
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###
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length = self._r_length.storage
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offset = self._r_offset.storage
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done = Signal(reset=1)
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ongoing = Signal()
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cnt = Signal(max=depth)
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fifo = SyncFIFO([("d", width)], depth)
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self.submodules += fifo
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# Write fifo is done only when done = 0
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# Fifo must always be pulled by software between
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# acquisition (Todo: add a flush funtionnality)
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self.comb +=[
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fifo.sink.stb.eq(self.sink.stb & ~done),
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fifo.sink.payload.d.eq(self.sink.payload.d),
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self.sink.ack.eq(1)
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]
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# Done, Ongoing:
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# 0, 0 : Storage triggered but hit was not yet seen
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# Data are recorded to fifo, if "offset" datas
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# in the fifo, ack is set on fifo.source to
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# store only "offset" datas.
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#
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# 0, 1 : Hit was seen, ack is no longer set on fifo.source
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# we are storing "length"-"offset" data in this
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# phase
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#
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# 1, 0 : We have stored "length" datas in fifo. Write to
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# fifo is disabled.
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# Software must now read data from the fifo until
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# it is empty
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# done & ongoing
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self.sync += [
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If(self._r_trigger.re & self._r_trigger.r, done.eq(0)
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).Elif(cnt==length, done.eq(1)),
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If(self.sink.stb & self.sink.payload.hit & ~done, ongoing.eq(1)
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).Elif(done, ongoing.eq(0)),
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]
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# fifo ack & csr connection
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self.comb += [
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If(~done & ~ongoing & (cnt >= offset), fifo.source.ack.eq(1)
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).Else(fifo.source.ack.eq(self._r_read_en.re & self._r_read_en.r)),
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self._r_read_empty.status.eq(~fifo.source.stb),
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self._r_read_dat.status.eq(fifo.source.payload.d),
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self._r_done.status.eq(done)
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]
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# cnt
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self.sync += [
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If(done == 1,
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cnt.eq(0)
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).Elif(fifo.sink.stb & fifo.sink.ack & ~(fifo.source.stb & fifo.source.ack),
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cnt.eq(cnt+1),
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)
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] |