Florent Kermarrec 500e58ce7d mibuild/platform/versa: fix clock_constraints		2015-03-17 15:25:10 +01:00
..
altera
lattice	mibuild/lattice: use ODDRXD1 and new synthesis directive	2015-03-17 14:59:36 +01:00
platforms	mibuild/platform/versa: fix clock_constraints	2015-03-17 15:25:10 +01:00
sim
xilinx	mibuild/xilinx/common: add XilinxDDROutput	2015-03-16 22:53:05 +01:00
__init__.py
generic_platform.py	fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code	2015-03-17 00:40:26 +01:00
generic_programmer.py
tools.py