35 lines
1.0 KiB
Python
35 lines
1.0 KiB
Python
from migen.fhdl.structure import *
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class Register:
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def __init__(self, name, raw=None):
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self.name = name
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self.raw = raw
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if raw is not None:
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self.dev_re = Signal(name=name + "_re")
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self.dev_r = Signal(raw, name + "_r")
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self.dev_w = Signal(raw, name + "_w")
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else:
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self.fields = []
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def add_field(self, f):
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self.fields.append(f)
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(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
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class Field:
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def __init__(self, parent, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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self.parent = parent
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self.name = name
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self.size = size
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self.access_bus = access_bus
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self.access_dev = access_dev
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self.reset = reset
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fullname = parent.name + "_" + name
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self.storage = Signal(BV(self.size), fullname)
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if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
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self.dev_r = Signal(BV(self.size), fullname + "_r")
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if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
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self.dev_w = Signal(BV(self.size), fullname + "_w")
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self.dev_we = Signal(name=fullname + "_we")
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self.parent.add_field(self)
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