Jędrzej Boczar 50805797c6 soc/software/liblitedram: optional write latency calibration debug output		2021-05-17 14:49:30 +02:00
..
build	lattice/programmer.py: Add iCESugar programmer	2021-05-07 10:55:48 +07:00
compat	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	soc/software/liblitedram: optional write latency calibration debug output	2021-05-17 14:49:30 +02:00
tools	tools/litex_server/litex_term: Add --jtag-chain argument.	2021-05-06 15:41:25 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00