121 lines
3.5 KiB
Python
121 lines
3.5 KiB
Python
# Simple Processor Interface
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from migen.fhdl.structure import *
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from migen.bank.description import *
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from migen.flow.actor import *
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# layout is a list of tuples, either:
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# - (name, bv, [reset value], [alignment bits])
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# - (name, sublayout)
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def _convert_layout(layout):
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r = []
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for element in layout:
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if isinstance(element[1], list):
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r.append((element[0], _convert_layout(element[1])))
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else:
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r.append((element[0], element[1]))
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return r
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def _create_registers_assign(layout, target, atomic, prefix=""):
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registers = []
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assigns = []
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for element in layout:
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if isinstance(element[1], list):
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r_registers, r_assigns = _create_registers_assign(element[1],
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atomic,
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getattr(target, element[0]),
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element[0] + "_")
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registers += r_registers
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assigns += r_assigns
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else:
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name = element[0]
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bv = element[1]
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if len(element) > 2:
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reset = element[2]
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else:
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reset = 0
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if len(element) > 3:
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alignment = element[3]
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else:
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alignment = 0
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reg = RegisterField(prefix + name, bv.width + alignment,
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reset=reset, atomic_write=atomic)
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registers.append(reg)
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assigns.append(getattr(target, name).eq(reg.field.r[alignment:]))
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return registers, assigns
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(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
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class SingleGenerator(Actor):
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def __init__(self, layout, mode):
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self._mode = mode
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super().__init__(("source", Source, _convert_layout(layout)))
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self._registers, self._assigns = _create_registers_assign(layout,
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self.token("source"), self._mode != MODE_SINGLE_SHOT)
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if mode == MODE_EXTERNAL:
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self.trigger = Signal()
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elif mode == MODE_SINGLE_SHOT:
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shoot = RegisterRaw("shoot")
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self._registers.insert(0, shoot)
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self.trigger = shoot.re
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elif mode == MODE_CONTINUOUS:
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enable = RegisterField("enable")
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self._registers.insert(0, enable)
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self.trigger = enable.field.r
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else:
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raise ValueError
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def get_registers(self):
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return self._registers
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def get_fragment(self):
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stb = self.endpoints["source"].stb
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ack = self.endpoints["source"].ack
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comb = [
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self.busy.eq(stb)
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]
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stmts = [stb.eq(self.trigger)] + self._assigns
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sync = [If(ack | ~stb, *stmts)]
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return Fragment(comb, sync)
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class Collector(Actor):
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def __init__(self, layout, depth=1024):
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super().__init__(("sink", Sink, layout))
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self._depth = depth
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self._dw = sum(len(s) for s in self.token("sink").flatten())
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self._reg_wa = RegisterField("write_address", bits_for(self._depth-1), access_bus=READ_WRITE, access_dev=READ_WRITE)
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self._reg_wc = RegisterField("write_count", bits_for(self._depth), access_bus=READ_WRITE, access_dev=READ_WRITE, atomic_write=True)
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self._reg_ra = RegisterField("read_address", bits_for(self._depth-1), access_bus=READ_WRITE, access_dev=READ_ONLY)
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self._reg_rd = RegisterField("read_data", self._dw, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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def get_registers(self):
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return [self._reg_wa, self._reg_wc, self._reg_ra, self._reg_rd]
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def get_fragment(self):
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mem = Memory(self._dw, self._depth)
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wp = mem.get_port(write_capable=True)
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rp = mem.get_port()
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comb = [
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If(self._reg_wc.field.r != 0,
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self.endpoints["sink"].ack.eq(1),
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If(self.endpoints["sink"].stb,
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self._reg_wa.field.we.eq(1),
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self._reg_wc.field.we.eq(1),
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wp.we.eq(1)
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)
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),
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self._reg_wa.field.w.eq(self._reg_wa.field.r + 1),
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self._reg_wc.field.w.eq(self._reg_wc.field.r - 1),
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wp.adr.eq(self._reg_wa.field.r),
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wp.dat_w.eq(Cat(*self.token("sink").flatten())),
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rp.adr.eq(self._reg_ra.field.r),
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self._reg_rd.field.w.eq(rp.dat_r)
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]
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return Fragment(comb, memories=[mem])
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