77 lines
1.8 KiB
Python
77 lines
1.8 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr
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from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
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import constraints
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MHz = 1000000
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clk_freq = 80*MHz
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sram_size = 4096 # in bytes
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l2_size = 8192 # in bytes
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def get():
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#
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# ASMI
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#
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asmihub0 = asmibus.Hub(24, 64, 8) # TODO: get hub from memory controller
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asmiport_wb = asmihub0.get_port()
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asmihub0.finalize()
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#
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# WISHBONE
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#
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cpu0 = lm32.LM32()
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norflash0 = norflash.NorFlash(25, 12)
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sram0 = sram.SRAM(sram_size//4)
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wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
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wishbone2csr0 = wishbone2csr.WB2CSR()
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# norflash 0x00000000 (shadow @0x80000000)
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# SRAM/debug 0x10000000 (shadow @0x90000000)
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# USB 0x20000000 (shadow @0xa0000000)
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# Ethernet 0x30000000 (shadow @0xb0000000)
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# SDRAM 0x40000000 (shadow @0xc0000000)
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# CSR bridge 0x60000000 (shadow @0xe0000000)
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wishbonecon0 = wishbone.InterconnectShared(
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[
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cpu0.ibus,
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cpu0.dbus
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], [
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(binc("000"), norflash0.bus),
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(binc("001"), sram0.bus),
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(binc("10"), wishbone2asmi0.wishbone),
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(binc("11"), wishbone2csr0.wishbone)
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],
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register=True,
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offset=1)
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#
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# CSR
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#
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uart0 = uart.UART(0, clk_freq, baud=115200)
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
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#
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# Interrupts
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#
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interrupts = Fragment([
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cpu0.interrupt[0].eq(uart0.events.irq)
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])
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#
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# Housekeeping
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#
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clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
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reset0 = m1reset.M1Reset()
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frag = autofragment.from_local() + interrupts
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src_verilog, vns = verilog.convert(frag,
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{clkfx_sys.clkin, reset0.trigger_reset},
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name="soc",
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clk_signal=clkfx_sys.clkout,
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rst_signal=reset0.sys_rst,
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return_ns=True)
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src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
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return (src_verilog, src_ucf)
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