52 lines
1.7 KiB
Python
52 lines
1.7 KiB
Python
from liteeth.common import *
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from liteeth.mac.core import LiteEthMACCore
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from liteeth.mac.frontend import wishbone
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthMACDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_phy_description(8),
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eth_mac_description(8),
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mac_header,
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mac_header_length)
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class LiteEthMACPacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_phy_description(8),
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mac_header,
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mac_header_length)
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class LiteEthMAC(Module, AutoCSR):
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def __init__(self, phy, dw, interface="mac", endianness="be",
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with_hw_preamble_crc=True):
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self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_hw_preamble_crc)
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self.csrs = None
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if interface == "mac":
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packetizer = LiteEthMACPacketizer()
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depacketizer = LiteEthMACDepacketizer()
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self.submodules += packetizer, depacketizer
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self.comb += [
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Record.connect(packetizer.source, self.core.sink),
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Record.connect(self.core.source, depacketizer.sink)
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]
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self.sink, self.source = packetizer.sink, depacketizer.source
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elif interface == "wishbone":
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self.submodules.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2)
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self.comb += [
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Record.connect(self.interface.source, self.core.sink),
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Record.connect(self.core.source, self.interface.sink)
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]
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self.ev, self.bus = self.interface.sram.ev, self.interface.bus
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self.csrs = self.interface.get_csrs()
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elif interface == "dma":
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raise NotImplementedError
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else:
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raise ValueError(inteface + " not supported by LiteEthMac!")
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def get_csrs(self):
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return self.csrs
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