165 lines
3.9 KiB
Python
165 lines
3.9 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.flow.actor import *
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from migen.genlib.buffers import ReorderBuffer
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class SequentialReader(Module):
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def __init__(self, port):
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assert(len(port.slots) == 1)
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self.address = Sink([("a", port.hub.aw)])
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self.data = Source([("d", port.hub.dw)])
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self.busy = Signal()
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###
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sample = Signal()
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data_reg_loaded = Signal()
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data_reg = Signal(port.hub.dw)
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accept_new = Signal()
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# We check that len(port.slots) == 1
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# and therefore we can assume that port.ack
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# goes low until the data phase.
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self.comb += [
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self.busy.eq(~data_reg_loaded | ~port.ack),
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port.adr.eq(self.address.payload.a),
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port.we.eq(0),
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accept_new.eq(~data_reg_loaded | self.data.ack),
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port.stb.eq(self.address.stb & accept_new),
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self.address.ack.eq(port.ack & accept_new),
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self.data.stb.eq(data_reg_loaded),
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self.data.payload.d.eq(data_reg)
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]
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self.sync += [
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If(self.data.ack, data_reg_loaded.eq(0)),
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If(sample,
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data_reg_loaded.eq(1),
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data_reg.eq(port.dat_r)
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),
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sample.eq(port.get_call_expression())
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]
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class OOOReader(Module):
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def __init__(self, port):
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assert(len(port.slots) > 1)
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self.address = Sink([("a", port.hub.aw)])
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self.data = Source([("d", port.hub.dw)])
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self.busy = Signal() # TODO: drive busy
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###
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tag_width = len(port.tag_call)
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data_width = port.hub.dw
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depth = len(port.slots)
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rob = ReorderBuffer(tag_width, data_width, depth)
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self.submodules += rob
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self.comb += [
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port.adr.eq(self.address.payload.a),
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port.we.eq(0),
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port.stb.eq(self.address.stb & rob.can_issue),
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self.address.ack.eq(port.ack & rob.can_issue),
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rob.issue.eq(self.address.stb & port.ack),
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rob.tag_issue.eq(port.base + port.tag_issue),
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rob.data_call.eq(port.dat_r),
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self.data.stb.eq(rob.can_read),
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rob.read.eq(self.data.ack),
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self.data.payload.d.eq(rob.data_read)
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]
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self.sync += [
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# Data is announced one cycle in advance.
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# Register the call to synchronize it with the data signal.
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rob.call.eq(port.call),
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rob.tag_call.eq(port.tag_call)
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]
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class SequentialWriter(Module):
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def __init__(self, port):
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assert(len(port.slots) == 1)
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self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
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self.busy = Signal()
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###
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data_reg = Signal(port.hub.dw)
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self.comb += [
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port.adr.eq(self.address_data.payload.a),
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port.we.eq(1),
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port.stb.eq(self.address_data.stb),
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self.address_data.ack.eq(port.ack),
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port.dat_wm.eq(0)
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]
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self.sync += [
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port.dat_w.eq(0),
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If(port.get_call_expression(),
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self.busy.eq(0),
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port.dat_w.eq(data_reg)
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),
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If(self.address_data.stb & self.address_data.ack,
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self.busy.eq(1),
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data_reg.eq(self.address_data.payload.d)
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)
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]
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class _WriteSlot(Module):
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def __init__(self, port, load_data, n):
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self.busy = Signal()
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###
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drive_data = Signal()
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data_reg = Signal(port.hub.dw)
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self.comb += [
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If(drive_data, port.dat_w.eq(data_reg)),
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port.dat_wm.eq(0)
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]
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self.sync += [
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drive_data.eq(0),
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If(port.get_call_expression(n),
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self.busy.eq(0),
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drive_data.eq(1)
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),
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If(port.stb & port.ack & (port.tag_issue == n),
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self.busy.eq(1),
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data_reg.eq(load_data)
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),
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]
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class OOOWriter(Module):
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def __init__(self, port):
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assert(len(port.slots) > 1)
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self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
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self.busy = Signal()
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###
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self.comb += [
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port.adr.eq(self.address_data.payload.a),
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port.we.eq(1),
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port.stb.eq(self.address_data.stb),
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self.address_data.ack.eq(port.ack)
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]
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busy = 0
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for i in range(len(port.slots)):
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write_slot = _WriteSlot(port, self.address_data.payload.d, i)
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self.submodules += write_slot
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busy = busy | write_slot.busy
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self.comb += self.busy.eq(busy)
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def Reader(port):
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if len(port.slots) == 1:
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return SequentialReader(port)
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else:
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return OOOReader(port)
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def Writer(port):
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if len(port.slots) == 1:
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return SequentialWriter(port)
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else:
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return OOOWriter(port)
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