336 lines
8.5 KiB
Python
336 lines
8.5 KiB
Python
from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy, PureSimulable
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class FinalizeError(Exception):
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pass
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(SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3)
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class Slot:
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def __init__(self, aw, time):
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self.state = Signal(BV(2))
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self.we = Signal()
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self.adr = Signal(BV(aw))
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self.time = time
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if self.time:
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self._counter = Signal(BV(bits_for(time)))
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self.mature = Signal()
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self.allocate = Signal()
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self.allocate_we = Signal()
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self.allocate_adr = Signal(BV(aw))
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self.process = Signal()
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self.call = Signal()
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def get_fragment(self):
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comb = []
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sync = [
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If(self.allocate,
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self.state.eq(SLOT_PENDING),
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self.we.eq(self.allocate_we),
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self.adr.eq(self.allocate_adr)
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),
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If(self.process, self.state.eq(SLOT_PROCESSING)),
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If(self.call, self.state.eq(SLOT_EMPTY))
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]
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if self.time:
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comb += [
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self.mature.eq(self._counter == 0)
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]
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sync += [
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If(self.allocate,
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self._counter.eq(self.time)
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).Elif(self._counter != 0,
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self._counter.eq(self._counter - 1)
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)
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]
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return Fragment(comb, sync)
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class Port:
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def __init__(self, hub, nslots):
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self.hub = hub
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self.slots = [Slot(self.hub.aw, self.hub.time) for i in range(nslots)]
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self.finalized = False
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# request issuance
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self.adr = Signal(BV(self.hub.aw))
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self.we = Signal()
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self.stb = Signal()
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# tag_issue is created by finalize()
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self.ack = Signal()
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# request completion
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self.call = Signal()
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# tag_call is created by finalize()
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self.dat_r = Signal(BV(self.hub.dw))
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self.dat_w = Signal(BV(self.hub.dw))
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self.dat_wm = Signal(BV(self.hub.dw//8))
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def finalize(self, tagbits, base):
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if self.finalized:
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raise FinalizeError
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self.finalized = True
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self.tagbits = tagbits
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self.base = base
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nslots = len(self.slots)
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if nslots > 1:
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self.tag_issue = Signal(BV(bits_for(nslots-1)))
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self.tag_call = Signal(BV(tagbits))
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def get_call_expression(self, slotn=0):
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if not self.finalized:
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raise FinalizeError
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return self.call \
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& (self.tag_call == Constant(self.base + slotn, BV(self.tagbits)))
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def get_fragment(self):
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if not self.finalized:
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raise FinalizeError
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slots_fragment = sum([s.get_fragment() for s in self.slots], Fragment())
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comb = []
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sync = []
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# allocate
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for s in self.slots:
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comb += [
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s.allocate_we.eq(self.we),
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s.allocate_adr.eq(self.adr)
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]
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choose_slot = None
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needs_tags = len(self.slots) > 1
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for n, s in reversed(list(enumerate(self.slots))):
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choose_slot = If(s.state == SLOT_EMPTY,
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s.allocate.eq(self.stb),
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self.tag_issue.eq(n) if needs_tags else None
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).Else(choose_slot)
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comb.append(choose_slot)
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comb.append(self.ack.eq(optree("|",
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[s.state == SLOT_EMPTY for s in self.slots])))
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# call
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comb += [s.call.eq(self.get_call_expression(n))
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for n, s in enumerate(self.slots)]
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return slots_fragment + Fragment(comb, sync)
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class Hub:
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def __init__(self, aw, dw, time=0):
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self.aw = aw
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self.dw = dw
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self.time = time
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self.ports = []
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self.finalized = False
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self.call = Signal()
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# tag_call is created by finalize()
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self.dat_r = Signal(BV(self.dw))
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self.dat_w = Signal(BV(self.dw))
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self.dat_wm = Signal(BV(self.dw//8))
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def get_port(self, nslots=1):
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if self.finalized:
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raise FinalizeError
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new_port = Port(self, nslots)
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self.ports.append(new_port)
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return new_port
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def finalize(self):
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if self.finalized:
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raise FinalizeError
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self.finalized = True
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nslots = sum([len(port.slots) for port in self.ports])
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tagbits = bits_for(nslots-1)
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base = 0
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for port in self.ports:
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port.finalize(tagbits, base)
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base += len(port.slots)
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self.tag_call = Signal(BV(tagbits))
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def get_slots(self):
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if not self.finalized:
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raise FinalizeError
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return sum([port.slots for port in self.ports], [])
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def get_fragment(self):
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if not self.finalized:
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raise FinalizeError
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ports = sum([port.get_fragment() for port in self.ports], Fragment())
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comb = []
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for port in self.ports:
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comb += [
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port.call.eq(self.call),
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port.tag_call.eq(self.tag_call),
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port.dat_r.eq(self.dat_r)
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]
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comb += [
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self.dat_w.eq(optree("|", [port.dat_w for port in self.ports])),
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self.dat_wm.eq(optree("|", [port.dat_wm for port in self.ports]))
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]
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return ports + Fragment(comb)
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class Tap(PureSimulable):
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def __init__(self, hub, handler=print):
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self.hub = hub
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self.handler = handler
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self.tag_to_transaction = dict()
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self.transaction = None
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def do_simulation(self, s):
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hub = Proxy(s, self.hub)
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# Pull any data announced in the previous cycle.
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if isinstance(self.transaction, TWrite):
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self.transaction.data = hub.dat_w
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self.transaction.sel = ~hub.dat_wm
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self.handler(self.transaction)
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self.transaction = None
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if isinstance(self.transaction, TRead):
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self.transaction.data = hub.dat_r
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self.handler(self.transaction)
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self.transaction = None
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# Tag issue. Transaction objects are created here
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# and placed into the tag_to_transaction dictionary.
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for tag, slot in enumerate(self.hub.get_slots()):
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if s.rd(slot.allocate):
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adr = s.rd(slot.allocate_adr)
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we = s.rd(slot.allocate_we)
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if we:
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transaction = TWrite(adr)
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else:
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transaction = TRead(adr)
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transaction.latency = s.cycle_counter
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self.tag_to_transaction[tag] = transaction
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# Tag call.
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if hub.call:
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transaction = self.tag_to_transaction[hub.tag_call]
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transaction.latency = s.cycle_counter - transaction.latency + 1
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self.transaction = transaction
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class Initiator(PureSimulable):
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def __init__(self, generator, port):
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self.generator = generator
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self.port = port
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self.done = False
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self._exe = None
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def _execute(self, s, generator, port):
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while True:
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transaction = next(generator)
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transaction_start = s.cycle_counter
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if transaction is None:
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yield
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else:
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# tag phase
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s.wr(port.adr, transaction.address)
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if isinstance(transaction, TWrite):
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s.wr(port.we, 1)
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else:
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s.wr(port.we, 0)
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s.wr(port.stb, 1)
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yield
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while not s.rd(port.ack):
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yield
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if hasattr(port, "tag_issue"):
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tag = s.rd(port.tag_issue)
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else:
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tag = 0
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tag += port.base
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s.wr(port.stb, 0)
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# data phase
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while not (s.rd(port.call) and (s.rd(port.tag_call) == tag)):
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yield
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if isinstance(transaction, TWrite):
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s.wr(port.dat_w, transaction.data)
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s.wr(port.dat_wm, ~transaction.sel)
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yield
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s.wr(port.dat_w, 0)
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s.wr(port.dat_wm, 0)
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else:
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yield
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transaction.data = s.rd(port.dat_r)
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transaction.latency = s.cycle_counter - transaction_start - 1
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def do_simulation(self, s):
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if not self.done:
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if self._exe is None:
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self._exe = self._execute(s, self.generator, self.port)
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try:
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next(self._exe)
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except StopIteration:
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self.done = True
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class TargetModel:
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def __init__(self):
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self.last_slot = 0
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def read(self, address):
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return 0
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def write(self, address, data, mask):
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pass
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# Round-robin scheduling.
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def select_slot(self, pending_slots):
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if not pending_slots:
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return -1
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self.last_slot += 1
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if self.last_slot > max(pending_slots):
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self.last_slot = 0
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while self.last_slot not in pending_slots:
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self.last_slot += 1
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return self.last_slot
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class Target(PureSimulable):
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def __init__(self, model, hub):
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self.model = model
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self.hub = hub
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self._calling_tag = -1
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self._write_request_d = -1
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self._write_request = -1
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self._read_request = -1
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def do_simulation(self, s):
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slots = self.hub.get_slots()
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# Data I/O
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if self._write_request >= 0:
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self.model.write(self._write_request,
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s.rd(self.hub.dat_w), s.rd(self.hub.dat_wm))
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if self._read_request >= 0:
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s.wr(self.hub.dat_r, self.model.read(self._read_request))
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# Request pipeline
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self._read_request = -1
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self._write_request = self._write_request_d
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self._write_request_d = -1
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# Examine pending slots and possibly choose one.
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# Note that we do not use the SLOT_PROCESSING state here.
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# Selected slots are immediately called.
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pending_slots = set()
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for tag, slot in enumerate(slots):
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if tag != self._calling_tag and s.rd(slot.state) == SLOT_PENDING:
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pending_slots.add(tag)
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slot_to_call = self.model.select_slot(pending_slots)
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# Call slot.
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if slot_to_call >= 0:
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slot = slots[slot_to_call]
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s.wr(self.hub.call, 1)
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s.wr(self.hub.tag_call, slot_to_call)
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self._calling_tag = slot_to_call
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if s.rd(slot.we):
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self._write_request_d = s.rd(slot.adr)
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else:
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self._read_request = s.rd(slot.adr)
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else:
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s.wr(self.hub.call, 0)
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self._calling_tag = -1
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