99 lines
2.5 KiB
Python
99 lines
2.5 KiB
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.bank.description import *
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from migen.actorlib.fifo import AsyncFIFO
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from miscope.std import *
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from miscope.trigger import Trigger
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from miscope.storage import Recorder, RunLengthEncoder
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from mibuild.tools import write_to_file
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def _getattr_all(l, attr):
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it = iter(l)
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r = getattr(next(it), attr)
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for e in it:
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if getattr(e, attr) != r:
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raise ValueError
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return r
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class MiLa(Module, AutoCSR):
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def __init__(self, depth, dat, with_rle=False, clk_domain="sys", pipe=False):
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self.depth = depth
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self.with_rle = with_rle
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self.clk_domain = clk_domain
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self.pipe = pipe
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self.ports = []
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self.width = flen(dat)
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self.stb = Signal(reset=1)
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self.dat = dat
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def add_port(self, port_class):
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port = port_class(self.width)
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self.ports.append(port)
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def do_finalize(self):
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stb = self.stb
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dat = self.dat
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if self.pipe:
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sync = getattr(self.sync, self.clk_domain)
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stb_new = Signal()
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dat_new = Signal(flen(dat))
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sync += [
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stb_new.eq(stb),
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dat_new.eq(dat)
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]
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stb = stb_new
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dat = dat_new
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if self.clk_domain is not "sys":
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fifo = AsyncFIFO([("dat", self.width)], 32)
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self.submodules += RenameClockDomains(fifo, {"write": self.clk_domain, "read": "sys"})
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self.comb += [
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fifo.sink.stb.eq(stb),
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fifo.sink.dat.eq(dat)
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]
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sink = Record(dat_layout(self.width))
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self.comb += [
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sink.stb.eq(fifo.source.stb),
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sink.dat.eq(fifo.source.dat),
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fifo.source.ack.eq(1)
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]
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else:
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sink = Record(dat_layout(self.width))
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self.comb += [
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sink.stb.eq(stb),
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sink.dat.eq(dat)
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]
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self.trigger = trigger = Trigger(self.width, self.ports)
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self.recorder = recorder = Recorder(self.width, self.depth)
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self.comb += [
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sink.connect(trigger.sink),
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trigger.source.connect(recorder.trig_sink)
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]
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if self.with_rle:
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self.rle = rle = RunLengthEncoder(self.width)
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self.comb += [
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sink.connect(rle.sink),
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rle.source.connect(recorder.dat_sink)
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]
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else:
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self.comb += sink.connect(recorder.dat_sink)
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def export(self, design, layout, filename):
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ret, ns = verilog.convert(design, return_ns=True)
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r = ""
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def format_line(*args):
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return ",".join(args) + "\n"
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r += format_line("config", "width", str(self.width))
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r += format_line("config", "depth", str(self.depth))
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r += format_line("config", "with_rle", str(int(self.with_rle)))
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for e in layout:
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r += format_line("layout", ns.get_name(e), str(flen(e)))
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write_to_file(filename, r)
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