Florent Kermarrec 54a4e6c1f6 cpu/femtorv: Rewrite FemtoRV Mem Bus to Wishbone adaption (thanks @BrunoLevy for the FemtoRV bus clarifications). ... Fixes the SDRAM accesses :)		2021-11-19 15:43:15 +01:00
..
build	build/efinix: Add InterfaceWriterBlock/InterfaceWriterXMLBlock and remove DRAM specific block/xml block generation.	2021-11-16 17:40:33 +01:00
compat	soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py.	2021-07-29 18:48:03 +02:00
gen	fhdl/verilog: Fix sig.direction regression.	2021-10-31 23:40:11 +01:00
soc	cpu/femtorv: Rewrite FemtoRV Mem Bus to Wishbone adaption (thanks @BrunoLevy for the FemtoRV bus clarifications).	2021-11-19 15:43:15 +01:00
tools	tools/litex_client: Add --length parameter for MMAP read accesses.	2021-10-22 09:07:19 +02:00
__init__.py	get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.	2021-09-28 16:27:13 +02:00