litex/misoclib
Florent Kermarrec 5516a49696 litesata: add doc for frontend 2015-05-06 03:57:07 +02:00
..
com liteusb: add simple example design with wishbone bridge and software to control it 2015-05-02 18:21:18 +02:00
cpu misoclib/cpu: merge git.py in identifier 2015-05-02 18:42:33 +02:00
mem litesata: add doc for frontend 2015-05-06 03:57:07 +02:00
others cores: avoid having too much directories when possible (for simple cores or cores contained in a single file) 2015-05-02 16:22:33 +02:00
soc soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment... 2015-05-04 12:28:49 +02:00
tools litescope/frontend/wishbone: add support for packetized mode 2015-05-02 16:22:43 +02:00
video global: more pep8 2015-04-13 18:02:26 +02:00
__init__.py rename milkymist-ng to MiSoC 2013-11-09 15:27:32 +01:00