136 lines
2.9 KiB
Python
136 lines
2.9 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.record import *
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from migen.genlib.misc import chooser
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from migen.genlib.crc import *
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from migen.flow.actor import Sink, Source
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class CRCInserter(Module):
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"""CRC Inserter
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Append a CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input without CRC.
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source : out
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Packets output with CRC.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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self.submodules.crc = crc_class(dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.crc.reset.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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self.crc.ce.eq(sink.stb & source.ack),
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self.crc.d.eq(sink.d),
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Record.connect(sink, source),
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source.eop.eq(0),
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If(sink.stb & sink.eop & source.ack,
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NextState("INSERT"),
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)
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)
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ratio = self.crc.width//dw
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt_done = Signal()
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fsm.act("INSERT",
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source.stb.eq(1),
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chooser(self.crc.value, cnt, source.d, reverse=True),
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If(cnt_done,
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source.eop.eq(1),
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If(source.ack, NextState("IDLE"))
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)
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)
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self.comb += cnt_done.eq(cnt == 0)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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cnt.eq(cnt.reset)
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).Elif(fsm.ongoing("INSERT") & ~cnt_done,
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cnt.eq(cnt - source.ack)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Inserter(CRCInserter):
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def __init__(self, layout):
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CRCInserter.__init__(self, CRC32, layout)
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class CRCChecker(Module):
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"""CRC Checker
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Check CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input with CRC.
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source : out
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Packets output with CRC and "error" set to 0
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on eop when CRC OK / set to 1 when CRC KO.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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self.submodules.crc = crc_class(dw)
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fsm = FSM(reset_state="RESET_CRC")
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self.submodules += fsm
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fsm.act("RESET_CRC",
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sink.ack.eq(0),
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self.crc.reset.eq(1),
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NextState("IDLE")
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)
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fsm.act("IDLE",
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sink.ack.eq(sink.stb),
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If(sink.stb & sink.sop,
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Record.connect(sink, source),
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self.crc.ce.eq(sink.ack),
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self.crc.d.eq(sink.d),
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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Record.connect(sink, source),
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self.crc.ce.eq(sink.stb & sink.ack),
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self.crc.d.eq(sink.d),
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source.error.eq(sink.eop & self.crc.error),
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If(sink.stb & sink.ack & sink.eop,
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NextState("RESET_CRC")
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Checker(CRCChecker):
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def __init__(self, layout):
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CRCChecker.__init__(self, CRC32, layout)
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