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5825ec8f47
litex
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litesata
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phy
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Florent Kermarrec
2bb9c6b649
add verilog backend to use the core with a "standard" flow
2015-01-19 20:38:48 +01:00
..
k7
clean up
2015-01-19 18:13:43 +01:00
__init__.py
add verilog backend to use the core with a "standard" flow
2015-01-19 20:38:48 +01:00
ctrl.py
refactor code
2015-01-17 13:22:52 +01:00
datapath.py
refactor code
2015-01-17 13:22:52 +01:00