142 lines
4.1 KiB
Python
142 lines
4.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.bus import wishbone
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from migen.corelogic.fsm import FSM
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from migen.corelogic.misc import split, displacer, chooser
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from migen.corelogic.record import Record
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# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
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class WB2ASMI:
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def __init__(self, cachesize, asmiport):
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self.wishbone = wishbone.Interface()
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self.cachesize = cachesize
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self.asmiport = asmiport
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if len(self.asmiport.slots) != 1:
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raise ValueError("ASMI port must have 1 slot")
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if self.asmiport.hub.dw <= 32:
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raise ValueError("ASMI data width must be strictly larger than 32")
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if (self.asmiport.hub.dw % 32) != 0:
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raise ValueError("ASMI data width must be a multiple of 32")
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def get_fragment(self):
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comb = []
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sync = []
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aaw = self.asmiport.hub.aw
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adw = self.asmiport.hub.dw
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# Split address:
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# TAG | LINE NUMBER | LINE OFFSET
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offsetbits = log2_int(adw//32)
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addressbits = aaw + offsetbits
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linebits = log2_int(self.cachesize) - offsetbits
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tagbits = addressbits - linebits
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adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
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# Data memory
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data_mem = Memory(adw, 2**linebits)
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data_port = data_mem.get_port(write_capable=True, we_granularity=8)
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write_from_asmi = Signal()
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write_to_asmi = Signal()
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adr_offset_r = Signal(offsetbits)
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comb += [
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data_port.adr.eq(adr_line),
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If(write_from_asmi,
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data_port.dat_w.eq(self.asmiport.dat_r),
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data_port.we.eq(Replicate(1, adw//8))
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).Else(
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data_port.dat_w.eq(Replicate(self.wishbone.dat_w, adw//32)),
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If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
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displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
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)
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),
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If(write_to_asmi, self.asmiport.dat_w.eq(data_port.dat_r)),
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self.asmiport.dat_wm.eq(0),
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chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
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]
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sync += [
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adr_offset_r.eq(adr_offset)
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]
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# Tag memory
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tag_mem = Memory(tagbits+1, 2**linebits)
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tag_port = tag_mem.get_port(write_capable=True)
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tag_layout = [("tag", tagbits), ("dirty", 1)]
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tag_do = Record(tag_layout)
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tag_di = Record(tag_layout)
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comb += [
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Cat(*tag_do.flatten()).eq(tag_port.dat_r),
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tag_port.dat_w.eq(Cat(*tag_di.flatten()))
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]
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comb += [
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tag_port.adr.eq(adr_line),
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tag_di.tag.eq(adr_tag),
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self.asmiport.adr.eq(Cat(adr_line, tag_do.tag))
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]
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# Control FSM
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write_to_asmi_pre = Signal()
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sync.append(write_to_asmi.eq(write_to_asmi_pre))
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fsm = FSM("IDLE", "TEST_HIT",
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"EVICT_ISSUE", "EVICT_WAIT",
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"REFILL_WRTAG", "REFILL_ISSUE", "REFILL_WAIT", "REFILL_COMPLETE")
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fsm.act(fsm.IDLE,
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If(self.wishbone.cyc & self.wishbone.stb, fsm.next_state(fsm.TEST_HIT))
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)
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fsm.act(fsm.TEST_HIT,
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If(tag_do.tag == adr_tag,
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self.wishbone.ack.eq(1),
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If(self.wishbone.we,
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tag_di.dirty.eq(1),
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tag_port.we.eq(1)
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),
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fsm.next_state(fsm.IDLE)
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).Else(
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If(tag_do.dirty,
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fsm.next_state(fsm.EVICT_ISSUE)
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).Else(
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fsm.next_state(fsm.REFILL_WRTAG)
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)
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)
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)
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fsm.act(fsm.EVICT_ISSUE,
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self.asmiport.stb.eq(1),
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self.asmiport.we.eq(1),
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If(self.asmiport.ack, fsm.next_state(fsm.EVICT_WAIT))
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)
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fsm.act(fsm.EVICT_WAIT,
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# Data is actually sampled by the memory controller in the next state.
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# But since the data memory has one cycle latency, it gets the data
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# at the address given during this cycle.
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If(self.asmiport.get_call_expression(),
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write_to_asmi_pre.eq(1),
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fsm.next_state(fsm.REFILL_WRTAG)
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)
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)
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fsm.act(fsm.REFILL_WRTAG,
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# Write the tag first to set the ASMI address
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tag_port.we.eq(1),
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fsm.next_state(fsm.REFILL_ISSUE)
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)
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fsm.act(fsm.REFILL_ISSUE,
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self.asmiport.stb.eq(1),
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If(self.asmiport.ack, fsm.next_state(fsm.REFILL_WAIT))
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)
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fsm.act(fsm.REFILL_WAIT,
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If(self.asmiport.get_call_expression(), fsm.next_state(fsm.REFILL_COMPLETE))
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)
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fsm.act(fsm.REFILL_COMPLETE,
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write_from_asmi.eq(1),
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fsm.next_state(fsm.TEST_HIT)
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)
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return Fragment(comb, sync, specials={data_mem, tag_mem}) \
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+ fsm.get_fragment()
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