49 lines
1.0 KiB
Verilog
49 lines
1.0 KiB
Verilog
/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module psync(
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input clk1,
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input i,
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input clk2,
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output o
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);
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reg level;
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always @(posedge clk1)
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if(i)
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level <= ~level;
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reg level1;
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reg level2;
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reg level3;
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always @(posedge clk2) begin
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level1 <= level;
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level2 <= level1;
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level3 <= level2;
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end
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assign o = level2 ^ level3;
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initial begin
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level <= 1'b0;
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level1 <= 1'b0;
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level2 <= 1'b0;
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level3 <= 1'b0;
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end
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endmodule
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