275 lines
8.1 KiB
Python
275 lines
8.1 KiB
Python
from migen.fhdl.structure import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.flow import plumbing
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from migen.actorlib import misc, dma_asmi, structuring, sim
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from migen.bank.description import *
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from migen.bank import csrgen
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_hbits = 11
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_vbits = 11
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_bpp = 32
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_bpc = 10
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_pixel_layout = [
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("b", BV(_bpc)),
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("g", BV(_bpc)),
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("r", BV(_bpc)),
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("pad", BV(_bpp-3*_bpc))
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]
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_bpc_dac = 8
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_dac_layout = [
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("hsync", BV(1)),
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("vsync", BV(1)),
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("b", BV(_bpc_dac)),
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("g", BV(_bpc_dac)),
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("r", BV(_bpc_dac))
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]
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class _FrameInitiator(Actor):
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def __init__(self, asmi_bits, length_bits, alignment_bits):
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self._alignment_bits = alignment_bits
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self._enable = RegisterField("enable")
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self._hres = RegisterField("hres", _hbits, reset=640)
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self._hsync_start = RegisterField("hsync_start", _hbits, reset=656)
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self._hsync_end = RegisterField("hsync_end", _hbits, reset=752)
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self._hscan = RegisterField("hscan", _hbits, reset=799)
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self._vres = RegisterField("vres", _vbits, reset=480)
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self._vsync_start = RegisterField("vsync_start", _vbits, reset=492)
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self._vsync_end = RegisterField("vsync_end", _vbits, reset=494)
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self._vscan = RegisterField("vscan", _vbits, reset=524)
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self._base = RegisterField("base", asmi_bits + self._alignment_bits)
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self._length = RegisterField("length", length_bits + self._alignment_bits, reset=640*480*4)
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layout = [
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("hres", BV(_hbits)),
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("hsync_start", BV(_hbits)),
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("hsync_end", BV(_hbits)),
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("hscan", BV(_hbits)),
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("vres", BV(_vbits)),
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("vsync_start", BV(_vbits)),
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("vsync_end", BV(_vbits)),
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("vscan", BV(_vbits)),
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("base", BV(asmi_bits)),
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("length", BV(length_bits))
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]
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super().__init__(("frame", Source, layout))
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def get_registers(self):
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return [self._enable,
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self._hres, self._hsync_start, self._hsync_end, self._hscan,
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self._vres, self._vsync_start, self._vsync_end, self._vscan,
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self._base, self._length]
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def get_fragment(self):
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# TODO: make address updates atomic
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token = self.token("frame")
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stb = self.endpoints["frame"].stb
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ack = self.endpoints["frame"].ack
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comb = [
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self.busy.eq(stb),
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token.hres.eq(self._hres.field.r),
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token.hsync_start.eq(self._hsync_start.field.r),
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token.hsync_end.eq(self._hsync_end.field.r),
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token.hscan.eq(self._hscan.field.r),
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token.vres.eq(self._vres.field.r),
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token.vsync_start.eq(self._vsync_start.field.r),
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token.vsync_end.eq(self._vsync_end.field.r),
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token.vscan.eq(self._vscan.field.r),
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token.length.eq(self._length.field.r[self._alignment_bits:])
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]
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sync = [
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If(ack | ~stb,
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stb.eq(self._enable.field.r),
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token.base.eq(self._base.field.r[self._alignment_bits:])
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)
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]
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return Fragment(comb, sync)
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class VTG(Actor):
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def __init__(self):
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super().__init__(
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("timing", Sink, [
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("hres", BV(_hbits)),
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("hsync_start", BV(_hbits)),
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("hsync_end", BV(_hbits)),
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("hscan", BV(_hbits)),
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("vres", BV(_vbits)),
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("vsync_start", BV(_vbits)),
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("vsync_end", BV(_vbits)),
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("vscan", BV(_vbits))]),
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("pixels", Sink, _pixel_layout),
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("dac", Source, _dac_layout)
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)
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def get_fragment(self):
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hactive = Signal()
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vactive = Signal()
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active = Signal()
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generate_en = Signal()
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hcounter = Signal(BV(_hbits))
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vcounter = Signal(BV(_vbits))
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skip = _bpc - _bpc_dac
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comb = [
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active.eq(hactive & vactive),
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If(active,
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self.token("dac").r.eq(self.token("pixels").r[skip:]),
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self.token("dac").g.eq(self.token("pixels").g[skip:]),
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self.token("dac").b.eq(self.token("pixels").b[skip:])
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),
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generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)),
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self.endpoints["pixels"].ack.eq(self.endpoints["dac"].ack & active),
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self.endpoints["dac"].stb.eq(generate_en)
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]
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tp = self.token("timing")
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sync = [
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self.endpoints["timing"].ack.eq(0),
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If(generate_en & self.endpoints["dac"].ack,
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hcounter.eq(hcounter + 1),
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If(hcounter == 0, hactive.eq(1)),
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If(hcounter == tp.hres, hactive.eq(0)),
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If(hcounter == tp.hsync_start, self.token("dac").hsync.eq(1)),
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If(hcounter == tp.hsync_end, self.token("dac").hsync.eq(0)),
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If(hcounter == tp.hscan,
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hcounter.eq(0),
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If(vcounter == tp.vscan,
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vcounter.eq(0),
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self.endpoints["timing"].ack.eq(1)
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).Else(
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vcounter.eq(vcounter + 1)
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)
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),
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If(vcounter == 0, vactive.eq(1)),
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If(vcounter == tp.vres, vactive.eq(0)),
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If(vcounter == tp.vsync_start, self.token("dac").vsync.eq(1)),
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If(vcounter == tp.vsync_end, self.token("dac").vsync.eq(0))
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)
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]
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return Fragment(comb, sync)
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class FIFO(Actor):
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def __init__(self):
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super().__init__(("dac", Sink, _dac_layout))
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self.vga_clk = Signal()
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self.vga_hsync_n = Signal()
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self.vga_vsync_n = Signal()
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self.vga_r = Signal(BV(_bpc_dac))
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self.vga_g = Signal(BV(_bpc_dac))
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self.vga_b = Signal(BV(_bpc_dac))
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def get_fragment(self):
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data_width = 2+3*_bpc_dac
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asfifo = Instance("asfifo",
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Instance.Parameter("data_width", data_width),
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Instance.Parameter("address_width", 8),
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Instance.Output("data_out", BV(data_width)),
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Instance.Output("empty", BV(1)),
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Instance.Input("read_en", BV(1)),
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Instance.Input("clk_read", self.vga_clk),
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Instance.Input("data_in", BV(data_width)),
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Instance.Output("full", BV(1)),
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Instance.Input("write_en", BV(1)),
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Instance.ClockPort("clk_write"),
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Instance.Input("rst", BV(1)))
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t = self.token("dac")
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return Fragment(
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[
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asfifo.get_io("read_en").eq(1),
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Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.get_io("data_out")),
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self.endpoints["dac"].ack.eq(~asfifo.get_io("full")),
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asfifo.get_io("write_en").eq(self.endpoints["dac"].stb),
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asfifo.get_io("data_in").eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
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self.busy.eq(0),
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asfifo.get_io("rst").eq(0)
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],
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instances=[asfifo])
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def sim_fifo_gen():
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while True:
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t = sim.Token("dac")
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yield t
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print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
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+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
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class Framebuffer:
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def __init__(self, address, asmiport, simulation=False):
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asmi_bits = asmiport.hub.aw
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alignment_bits = bits_for(asmiport.hub.dw//8) - 1
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length_bits = _hbits + _vbits + 2 - alignment_bits
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pack_factor = asmiport.hub.dw//_bpp
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packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
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fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
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adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
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adrbuffer = ActorNode(plumbing.Buffer)
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dma = ActorNode(dma_asmi.Reader(asmiport))
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datbuffer = ActorNode(plumbing.Buffer)
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cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
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unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
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vtg = ActorNode(VTG())
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if simulation:
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fifo = ActorNode(sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout)))
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else:
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fifo = ActorNode(FIFO())
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g = DataFlowGraph()
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g.add_connection(fi, adrloop, source_subr=["length", "base"])
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g.add_connection(adrloop, adrbuffer)
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g.add_connection(adrbuffer, dma)
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g.add_connection(dma, datbuffer)
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g.add_connection(datbuffer, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, vtg, sink_ep="pixels")
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g.add_connection(fi, vtg, sink_ep="timing", source_subr=[
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"hres", "hsync_start", "hsync_end", "hscan",
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"vres", "vsync_start", "vsync_end", "vscan"])
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g.add_connection(vtg, fifo)
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self._comp_actor = CompositeActor(g, debugger=False)
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self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
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address=address)
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# VGA clock input
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if not simulation:
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self.vga_clk = fifo.actor.vga_clk
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# Pads
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self.vga_psave_n = Signal()
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if not simulation:
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self.vga_hsync_n = fifo.actor.vga_hsync_n
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self.vga_vsync_n = fifo.actor.vga_vsync_n
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self.vga_sync_n = Signal()
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self.vga_blank_n = Signal()
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if not simulation:
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self.vga_r = fifo.actor.vga_r
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self.vga_g = fifo.actor.vga_g
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self.vga_b = fifo.actor.vga_b
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def get_fragment(self):
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comb = [
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self.vga_sync_n.eq(0),
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self.vga_psave_n.eq(1),
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self.vga_blank_n.eq(1)
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]
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return self.bank.get_fragment() \
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+ self._comp_actor.get_fragment() \
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+ Fragment(comb)
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